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Design techniques for high-speed low-power wireline receivers

University of British Columbia

High-speed data transmission through wireline links, either copper or optical based, has become the backbone for modern communication infrastructure. Since at multi-Gb/s data rates the transmitted signal is attenuated and distorted by the channel, sophisticated analog front-end and/or digital signal processing are required at the receiver (RX) to recover data and clock from the received signal. In this thesis, both analog- and digital-based receivers are investigated, and power-reduction techniques are exploited at both system- and circuit levels. A speculative successive-approximation register (speculative/SAR) digitization algorithm is proposed for use at the receiver front-end of digital receivers that combines equalization and data recovery with the digitization step at the front-end analog-to-digital converter (ADC). Furthermore, architecture for quadrature clock generation is proposed which is of use in both analog and digital receivers. Then, an analog clock and data recovery (CDR) architecture suitable for high data rates (e.g., beyond 10 Gb/s) is proposed that utilizes a wideband data phase generation technique to facilitate mixer-based phase detection. The CDR architecture is implemented and experimentally validated for a 12.5 Gb/s system. Finally, a mixed-mode hardware-efficient CDR architecture is proposed that exploits both analog and digital design techniques to reach a robust operation suited for long-haul optical link communications. Proof-of-concept prototypes of the proposed RX architectures are designed and implemented in 65 nm and 90 nm CMOS processes. The prototypes are successfully tested. Note that although individual performance merits of the each prototype may not necessarily outperform that of the state-of-the-art, however, the prototypes confirm the feasibility of the proposed structure. Furthermore, the proposed architectures can be used at higher data rates particularly if more advanced technologies with higher device transit frequency, (fT), is used.

Text

2013-07-16

Attribution-NonCommercial-NoDerivatives 4.0 International

http://hdl.handle.net/2429/44660

Electrical and Computer Engineering

University of British Columbia

UBCV

http://creativecommons.org/licenses/by-nc-nd/4.0/