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An ultra-low power SAR ADC Chang, Yin-Ting Melody 2009

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An Ultra-Low Power SAR ADCbyYin-Ting Melody ChangBASc., University of British Columbia, 2004A THESIS SUBMITTED IN PARTIAL FULFILLMENT OFTHE REQUIREMENTS FOR THE DEGREE OFMASTER OF APPLIED SCIENCEinTHE FACULTY OF GRADUATE STUDIES(Electrical and Computer Engineering)THE UNWERSITY OF BRITISH COLUMBIA(Vancouver)April 2009©Yin-Ting Melody Chang, 200911AbstractWireless sensor networks are used in variety of applications includingenvironmentalmonitoring, industrial control, healthcare, home automation,traffic control, and temperatureand pressure monitoring systems. Many one-timeuse wireless micro sensor applicationsrequire ultra-low-power devices due to the limited energy capacity andlifetime of theirsmall-size battery. Many sensor nodes require an analog-to-digitalconverter (ADC) toconvert the analog output of the sensor to digital forstorage and/or further processing. Inthis work, an 8-bit ultra-low-power successive approximation register(SAR) ADC ispresented that operates from a low power supply voltage of 1V. The circuitis implementedin a 0.18 tm bulk CMOS technology without using any10W-VT devices. In terms of activecomponents, this ADC requires one comparator, 18 D flip-flops, severalswitches, and onevoltage doubler. The ADC achieves an effective number of bits of 7, whileoperating with asampling rate of 1 OOkS/s and consuming 1.4 iW from a 1 V supply.Table of ContentsABSTRACT.11TABLE OF CONTENTSiiiLIST OF TABLESvLIST OF FICLJI{ESviACKNOWLEDGEMENTSviiiChapter 1 1’Iotivation11.1 Organization of the Thesis3Chapter 2 Background42.1 Ideal A/D Converter42.2 Quantization Noise62.3 Device Noise92.4 Power Supply Noise122.5 Other Non-idealities and Performance Limitation12Chapter 3 Circuit Design143.1 ADC Architecture153.2 Design Flow203.3 Reference Switch and Switching Network 243.4 Voltage Doubler283.5 Capacitor Array343.6 Switching Network 413.7 Comparator49111iv3.8 Successive Approximation Register50Chapter 4 Measurement Results524.1 Differential and Integral Nonlinearity534.2 Distortion Ratio and Effective number of bits564.3 Power Consumption58Chapter 5 Layout605.1 Device Matching615.2 Capacitor Matching and Necessary Dummies645.3 Latch-ups and Guard Rings65Chapter 6 Conclusions6970VList of TablesTable 3-1. Summary of switch resistance and settlingtime corresponds to 9-bit accurary. ..44Table 4-1. Figure of merit comparison table59Table 4-2. Summery of measured performance59viList of FiguresFigure 2-1 An ideal AID converter block diagram5Figure 2-2 Transfer function of an ideal 2bit ADC withoutquantization error 6Figure 2-3 Block diagram of a circuit investigatingquantization noise behaviour 7Figure 2-4 Quantization error plot with a ramp input7Figure 2-5 MOSFET noise11Figure 2-6 Non-ideality factors13Figure 3-1. Categoring of ADC architectures basedon the power consumption, resolutionand speed of ADCs (adapted from [14])16Figure 3-2 A N-bit charge redistribution successiveapproximation architecture 19Figure 3-3. Systematic flow of the search algorithmin a SAR ADC [13] 21Figure 3-4. SAR ADC at sampling phase22Figure 3-5. SAR ADC at bit conversion phase24Figure 3-6. Voltage range at Vincmp node of the SAR ADC25Figure 3-7. Voltage doubler with PMOS reference switch29Figure 3-8. Transient response of the voltage doubler30Figure 3-9. Circuit setup for DFT analysis31Figure 3-10. Waveform and DFT result on Vdd2 of voltage doubler32Figure 3-11. Voltage doubler switching time33Figure 3-12. Voltage doubler FFT33Figure 3-13. Parasitics capacitance extraction of unitcapacitor 38Figure 3-14. Common centroid layout for the capacitor array39Figure 3-15. The proposed layout floorplan for metal plate capacitorarray 41Figure 3-16. Simplified ADC block diagram with switching networkdiagram detail 42Figure 3-17. One technique for reducing the cause of chargeinjection by adding acomplementary NMOS switch47Figure 3-18. Another technique for reducing the causeof charge injection and clockfeedthrough48Figure 3-19. Comparator Schematic50Figure 3-20. 8-bit SAR schematic consists of 18 DFFs51viiFigure 4-1. ADC test setup.52Figure 4-2. Example of an ADC transfer function withDNL and ]NL 53Figure 4-3. Differential nonlinearity error of the ADC54Figure 4-4. Integral nonlinearity error of the ADC55Figure 4-5. Effective number of bits, ENOB, vs inputfrequency, fin57Figure 4-6. ENOB vs sampling frequency, fs57Figure 4-7. Power consumption measured at differentsampling frequencies 58Figure 5-1. Complete SAR ADC die micrograph withcircuit location noted 61Figure 5-2. A comparator layout63Figure 5-3. Capacitor array layout65Figure 5-4. Latch-up circuit model from a CMOS invertercross section [26) 66Figure 5-5. Latch-up circuit is re-drawn from figure5-4 67Figure 5-6. Guard rings prevent latch-up issues68viiiAcknowledgementsI would like to thank my supervisor, Dr.Shahriar Mirabbasi for giving me theopportunity towork in his group. Without his continuous supportand enthusiasm, this thesis wouldnot becompleted. My special thanks goes to Roberto Rosalesfor his endless help and support onmy chip testing. I would also like to acknowledgemy colleagues in System-On-a-Chipgroup in UBC, especially Amit Kedia, Dipanjan Sengupta,Samad Sheikhaei, MohammadHekmat, Shirley Au, and Howard Yang. Theymade my grad school life in UBC enjoyableand amazing. At the most, I would liketo thank my parents for their endless support andencouragement. Without their support and love, I wouldnot have gone this far for all theachievements for my life.1Chapter 1MotivationAnalog-to-digital converters (ADCs) are ubiquitousblocks that are used in almost allelectronic systems to convert physical analog signalsto digital data. Often, an ADC isaccompanied with a digital signal processor(DSP) to further process and manipulate data inthe digital domain. Current trends are to implementas much as the signal processing aspossible in the digital domain. Due to the relativelylow cost of transistors and digital logicin CMOS, this has made CMOS technology a primecandidate for circuit implementation.In the past, many researchers have focused on developing newADC architectures such asdelta-sigma [1] and pipeline converters [2], whichaim to push the performance limits ofADC in terms of resolution, speed, and power. Recently,there has been increasing interestin ultra-low power ADCs for use in battery poweredor self-sustaining systems such aswireless sensor network [3, 4].Potential applications of ultra-low-power ADCs arequite diverse: industrial monitoring,home appliance control, wildlife population tracking,weather pattern prediction, hearingaids, micro-robotic systems, and tire pressure monitoring system(TPMS), to name a few. Inlarge scale wireless sensor networks, power managementis important because many onetime use wireless micro-sensor nodes require ultra-low-powerdevices due to the limitedlifetime of their battery [5]. The average life time for a 1cm3 Lithium battery continuouslysupporting 100 iW power is one year [6]. It is also possibleto use energy harvesting2techniques to create a self-sufficient system, aslong as the power requirement of theelectronic circuitry is low enough. To satisfy these ultra-lowpower requirements, sensornetwork nodes must leverage both low cost CMOSdevice and micro-electromechanicalsystem (MEMS) technologies in order to integrate sensors, DSP, communicationblocks, andenergy sources into one ultra-low-power miniature sensor node.The ADC presented here is aimed for general wireless sensornetwork applications and inparticular for use in TPMS. In such applications, the ADC isthe interface block betweenthe environmental sensor and the processing unit. In thesesystems, not only the powerconsumption and standby power are critical, but alsothe performance of the ADC in termsof the required resolution is important. This work describes thedesign and implementationof an 8-bit successive-approximation register (SAR) ADC in a 0.18urnCMOS technology.The target supply voltage for this design is 1 V and the circuitperformance and powerconsumption are achieved without using any10W-VT devices. This work is based on thethesis work done by M. Scott [7]. The major differences betweenthis work and Scott’swork are the use of the metal sandwiched capacitors instead of poly-to-polycapacitor (aspoly-to-poly capacitors are not available in the 0.18umCMOS technology targeted in thiswork) the floorplan of the capacitor array, and the voltage doubler.This research is intended to develop an ultra-low power ADC in a0.18urn bulkCMOSprocess. It targets an ultra-low-power of few microwatts andlower wafer cost whichtranslate into avoiding the use of special mask layers such aslow-VT device mask or metalinsulator-metal capacitors. In this work, only the standard processis used. To achieve thegoal of ultra-low power, the individual blocks in the ADC need to be as simpleas possible.3The more transistors in the circuit, the more power willbe consumed at the moment whenthe transistors are being turned on/off. Also, the power consumptionis the product ofsupply voltage and the overall current that the circuit drawsfrom the supply. Consequently,lowering the power supply would be beneficialto for reducing the overall powerconsumption.1.1 Organization of the ThesisThis thesis is organized as follows: first, Chapter2 gives an overview of an ideal ADC andbriefly discusses its fundamental limitations. Next, Chapter3 discusses the ADCarchitecture used in this work, design flow and the circuit designof individual blocks of theADC. This chapter also analyzes the circuit designof each individual component. Chapter4 explains the evaluation of the ADC and provides thetest and measurement results from thefabricated chip.Chapter 5 explores some important layout techniquesused in this design and discusses thepotential latch-up issues that might damage the circuit and techniquesto minimize thepossibility of latch up. Finally, Chapter 6 presents concludingremarks and suggestions forfuture work.4Chapter 2BackgroundADCs are the interface block between the analog and the digitaldomains. Among theimportant trade-offs in an ADC, is that of betweenspeed and accuracy. The choice of anADC architecture depends on the application and the requirementsof the overall system. Inaddition, each architecture has its own limitation on different performancecriteria, such asspeed, power, and area. Nowadays, power consumption is oneof the important designspecifications in almost all applications. A good understandingof the fundamental limits ofADCs is necessary to achieve an ultra-low-power design. Thesefundamentals areoverviewed in this chapter.2.1 Ideal AID ConverterAn ideal A/D converter has an analog input (V1), reference signal(Vref), and digital outputs(B0), as shown in Figure 2-1. In most ADCs, a voltage quantity is used as an analog inputrather than a current quantity partly because it is usually easierto compare and storevoltages. However, some ADCs still use current quantities [14].5VinBoutVrefFigure 2-1 An ideal AID converter block diagramThe relationship between an analog input, reference signal, anddigital outputs can bepresented as the following equation:V=Vref(i*2’+b2*22+b3 *2-f-•••+bN*2’)2-1where, b1 is the most significant bit (MSB) andbN is the least significant bit (LSB). Thevoltage change that corresponds to the minimum step size changeat the output of the ADCis defined as VLSBVrefLSBN -A 2-bit ideal A/D converter transfer characteristic is presented below.6Bout11— —0.5Jref 0.75 VrefFigure 2-2 Transfer function of an ideal 2bit ADC without quantization errorAny deviation from the nominal input values that produces the same digitaloutput isreferred to as the quantization error. In other words, the difference betweenthe originalanalog input and the confined digital output is called quantizationerror, q. Note thatquantization error only exists in an ADC. There is no occurrence of quantizationerror in adigital-to-analog converter (DAC) because the output is well defined byspecific input bitvalues. The detail of quantization noise will be discussed in section Quantization NoiseThe digital outputs of an ADC represent quantized values of a continuous input signal.Thedifference between the actual analog value and their respective quantizedvalue is calledquantization noise.- ---- .-.-.-. — — —1 LSB100100— —I_0.25 Vref Vref7The quantization is a “many to one” mapping. That isa specific digital output codecorresponds to a range of analog input signal values. To illustratequantization noise, theoutput of an ideal ADC (Bout) is fed to an ideal DACso that the digital signal can betransformed back to the analog domain. The block diagramof this flow is shown in Figure2-3.VinFigure 2-3 Block diagram of a circuit investigating quantization noisebehaviourWhen a ramp input is applied at V in Figure 2-3, the resultingoutput of the DAC willappear as a staircase. The quantization error, q, is shown in Figure 2.4.1V2Analog input referenceefw0w0(‘3N(‘3D0Figure 2-4 Quantization error plot with a ramp input8The level of quantization noise decreases as the number of bits ofthe ADC increases. Thenumber of bits of the ADC is referred to as the ADC’s resolution. Quantizationnoise existsin all ADCs, including ideal ADCs. Usually, the input signal range is withinthe conversionrange, but it may go beyond or below the specified voltage range.Consequently, largeerrors may occur if the output is not confined to these limits.In order to approximate the power of the quantization noise, acommon simplifyingassumption is that the quantization error is independent of the analoginput and uniformlydistributed between —zV2 and +A12, where A is equal toVLSB. Although this assumption isnot always valid, it provides a reasonable approximation whenthe resolution of the ADC isabove 4 bits. With this assumption, the total quantization noise poweris given by[81:2D—‘QNoise1i+V,I2=—I eds 2-3v.l—VBI2qLSBy2— LSB12The full-scale signal-to-noise ratio (SNR) of the ADC is definedas the full-scale signalpower in the input divided by the quantization noise power in the output.To calculate thisSNR, a full-scale sinusoid input signal with amplitude of Vref/2 is applied.Using equations2-1 and 2-2, the input signal power is given by=Vf.22-4Given the input signal power and quantization noise power, the SNRis9PSNR= Ifl2Ut“QNoise2211_372= ‘LSB2-5V8/12=2212In decibels, the SNR becomes,SNR=6.02N+l.76 dB 2-6This SNR is often used to evaluate the performance of a given N-bitADC. This is themaximum SNR value that any N-bit ADC can achieve when the inputis sinusoid. However,in practice, this maximum SNR cannot be achieved dueto other noise sources,nonlinearities, and system limitations.2.3 Device NoiseThere are many sources of circuit noise that a designer has to take into considerationwhiledesigning a circuit. The presence of device noise is unavoidable in all real circuits.Devicenoise plays an important role in ADC design because it determines the performanceof theADC. Unlike the quantization noise which is a result of the analog-to-digital conversionprocess, a circuit designer can minimize device noise by using the appropriatecircuitarchitecture and design. A good circuit design can minimize the power of the circuit, whileachieving the desirable performance and limiting the level of the noise totolerable amounts.10The main forms of device noise in CMOS and bipolarjunction transistor (BJT) technologyare thermal noise, flicker noise, and shot noise.Thermal noise exists in transistors andresistors, flicker noise and shot noise exist in alltransistors and diodes with MOS transistorshaving higher levels of flicker noise as compared toBJTs. All of these noise sources willdegrade performance and limit the achievable resolutionof an ADC.Thermal noise is the most common and major device noiseappearing in most circuitsbecause it exists in both transistors and resistors. It isfound to be the small current causedby the thermal motion of the conduction electrons inthe resistive channels with a randomnoise which will increase with temperature. Thermalnoise is present in both conventionalresistors and distributed gate resistance in MOSFETs[9]. Due to the property of frequencyindependence, thermal noise is also called“white noise” for having a uniform powerspectrum.Flicker noise is another significant noise source appearing fromthe random trapping ofcharge at the oxide-silicon interface of MOSFETs.The noise spectral density is given by[10],K 1V = .— 2-7WLCOXfwhere K is a process-dependent constant,fis the frequency, W is the width of the transistor,L is the gate length of the transistor, and C0,is the gate oxidecapacitance per unit area. Thenoise spectral density is inversely proportional to thegate area and frequency. Therefore,flicker noise is also called 1/f noise. Due to theproperty of inverse relationship with11Figure 2-5 MOSFET noiseShot noise refers to the fluctuating current that is composed of discretecharge carrierscrossing the potential barrier at the semiconductor pn junction. Thecharge carriers can passthe barrier independently of one another at an average rate givenby the direct current flowin both diode and bipolar transistors; The spectral density of shot noise is givenby[121,i,210 =qkI0 A2 1Hzwhere q is the electron charge,L3 is the direct current flow through the junction, and k is theconstant that varies from device to device and depends on howthe junction is biased. Fromequation 2-8, shot noise is proportional to the direct current. Like thermalnoise, the shotnoise has a white frequency spectrum.frequency, flicker noise becomes the dominant noisesource at low frequencies. Figure 2-5shows a typical noise spectral density for a MOSFET [11].e.+ci— 10dB/decade1/f noise cornerThermal noise do mm atesf2-812In general, any type of noise source would degrade the achievableresolution of an ADC fora given amount of power consumption. While thermal,flicker, and shot noise contribute agreat deal of device noise, the total ADC noise still dependson the circuit architecture andthe technology which the circuit would be implemented in. Ina real circuit, device noisecan never be eliminated, but can be minimized withproper design. In addition to properdevice sizing and biasing, there are circuit techniques to minimizenoise, for examplechopper stabilization [13].2.4 Power Supply NoisePower supply noise arises when the power supplyis drifting or changing due tocurrent/voltage fluctuation in other parts of the chip. The currentfluctuations introducevoltage fluctuations across the series resistance and inductanceof the bondwires and pinsfrom the external supply to the core of circuitry. One approach to avoidthe power supplynoise is to design a supply independent reference voltageto be used asVDD for the rest ofthe circuits on chip. However, power consumption andarea will increase due to this extrastage. Another approach is to maximize the power supply rejectionratio of the entiresystem.2.5 Other Non-idealities and Performance LimitationIn practice, there are several important non-idealitiesthat can degrade the circuitperformance due to the imperfect circuits. Some of these non idealityfactors are shown inFigure 2-6: charge injection, gain, harmonic distortion, hysteresiserror, settling time, clock13skew and jitter. Most of the non-ideality errorsdepend on the circuit architecture andimplementation. Some arise from the systematic level and layout as well.For example, inamplifiers and comparators, random input offset is one of the imperfectionsdue to thevariations in the device. Process variation can be another non-linearity factorwhen the dieis fabricated.Process variationGain/Jitter Non-Ideality/Settling timeCharge injectionFigure 2-6 Non-ideality factorsThose errors are difficult to relate to the final resolution of the ADC dueto large variety oferror behaviours. The effect of each circuit non-ideality can be analyzedindividually onhow severe each factor can degrade the ADC performance. In general,circuit non-idealitycan be reduced with careful circuit design and layout. However, more powerconsumptionand devices might be required for reducing the effect of non-ideality. Thus, thereis a tradeoff between circuit performance, complexity, power consumption, and die area.14Chapter 3Circuit DesignThe process of designing ultra-low-power circuitsstarts with examining the powerconsumption of various circuit architectures. Thechoice of architecture is critical in thedesign process since a poor choice could leadto a sub-optimal design, no matter how welldesigned the sub-blocks are. On the other hand, a proper choiceof architecture can result innot only dramatic energy savings but also good performancewith respect to other metrics.Although power consumption is of paramount importance in this application,there are otherconsiderations that will affect the choice of architecture.In the target TPMS design, there will be a mainmodule in the car controlling the sensornode in each tire. Although each sensor node has very limited capabilityand functionality,the entire network system can still be powerful by utilizing the sensingand data processingpower of each individual node. Each sensor node has its ownhardware and embeddedsoftware, such as MEMS sensors, pre-amplifier,ADC, microprocessor, and a RFtransceiver. In distributed sensor networks, eachnode is designed to operate using verylittle energy and meeting the required performance specificationand communicating withthe main module or other nodes to exchange data.In our application, the ADC performance specificationis not particularly strict. Betterperformance can be achieved at the cost of more power dissipation.Each node has different15modes of operation such as sensing pressure or temperature.Due to the low voltage natureof this design, it is desirable for the ADC to have a rail-to-rail input conversionrange, anduse a pre-amplifier to scale the sensed voltage to the properinput range for ADC accordingto different modes. This would allow for a greater noise margin.In most ADCs, the circuitconsumes more power during the sampling phase anduses as little power as possible duringthe conversion phase. Therefore, power consumption canbe effectively minimized ifenergy saving techniques can be used during the sampling phase.In this TPMS application, the ADC is designed in a0.18 ,im CMOS technology withoutusing any 10W-VT devices. The threshold voltages for the NMOS and PMOSdevices aretypically around 0.5 V and -0.5 V, respectively. Metal-insulator-metalcapacitors (MIMcaps) are used to implement the capacitors in the voltage doubler design.The ADC wasdesigned to meet the following performance specifications:1. Resolution of 8-bits2. Input range equal to rail-to-rail3. Low supply voltage of 1 V4. Sampling rate greater than 50 kSample/s5. Power consumption less than or equal to 5 tW3.1 ADC ArchitectureThere are many types of ADC architectures. In Figure 3-1, major ADCarchitectures arecategorized in terms of power, resolution, and sampling rate. As shown inthe figure, only a16few architectures are suitable for the TPMS application.Since low power consumption is ofparamount importance for this design, the high-speed architectureswhich also have highpower dissipation characteristics are not suitable choices./Low PowerFigure 3-1. Categoring of ADC architectures based on the power consumption,resolution and speed ofADCs (adapted from [14])Time-interleaved converters usually require multiplesets of analog hardware such assample-and-hold circuits and sub-ADCs to segment the inputsignals. By splitting the inputsignal into segments, different portions of the signal canbe processed in parallel, thusreducing the time needed for conversion, however, the highpower consumption is adrawback [15]. Flash converters are generally known as the simplestand fastest architecture<MediumPower>1IntegratingOversamplingECIVSampling Rate17for implementing ADCs. In this type of converters,a resistive ladder divides the referencevoltage into2Ndifferent values which can be comparedin parallel with the analog input. Inorder to do the conversion in parallel,2Ncomparators are required [16]. This resultsin ahigh power dissipation and makes the flash converterimpractical for low power and highresolution designs. Folding and interpolating convertersare variants of flash converters andcontain less comparators while maintaininga relatively high speed of operation; however,the architecture still consumes too much power andis not suitable for this design [17]. Thearchitecture of two-step converters separatesthe task of most significant bit (MSB)conversion and the least significant bit (LSB)conversion [18]. This enables coarseresolution comparator to be used for MSB conversion whilethe fine resolution comparatoris used for LSB conversion. Pipeline converters are not suitablefor this application becausethey contain several comparison channels requiring excess amountof hardware, resulting inadditional power consumption.Integrating (dual slope) converters can become a viable architecturefor this application ifthey can achieve higher sampling rates. They have very low offsetand gain errors, and canachieve very linear outputs. This architecture consists of small amountof circuitry so it canbe very low power [14]. Two disadvantages of the integratingconverters are that theconversion speed is very slow and accurate clock timing isrequired. In the TPMSapplication, it is difficult to generate a high precision clock withoutconsuming excesspower. In our application, not only the slow conversionspeed of integrating converterscould be an issue, but also the conversion periodcould vary depending on the operationmode. Therefore, precise timing requirements and varyingconversion periods made18integrating converters unsuitable for this application,even though the power consumption ofthis architecture is very low.Oversampling converters are a popular approachfor high resolution medium-to-low speedapplications. They are also known as delta-sigmaADCs [14]. Delta-sigma ADCs can bemade to be low power for a given resolution and sampling rate.However, they requirecomplex clocking circuitry and for meeting the requiredspecification of this application thatwould need excess power.Algorithmic converters are one of the suitable architectures forthis application. Theyrequire a small amount of analog circuitry which consumesvery little power and they re-usethe same circuit to perform conversion cyclically over time. Duringthe conversion cycle, acomparator, two sample-and-hold circuits, and anamplifier with a gain of 2 are needed.Jniplementing an accurate multiply-by-two gain amplifiercan be one of the drawbacks.Fortunately, it is possible to design the gain amplifierso that it does not rely on anycapacitor matching [14]. Another drawback of this architecture isthat it cannot compare theinput against the reference voltage directly. The inputsignal always needs to be sampledtwice using the same capacitor and then use the gainof 2 amplifier to perform theconversion process. This process leads to a relatively slow conversionspeed. A 10-b cyclicalgorithmic with 1 iW power dissipation hasa sampling rate of 2.9 kS/s [19].The successive-approximation register (SAR) architecturepossesses all the desiredadvantage of algorithmic ADCs. In addition, it has theflexibility of performing comparisonon the input signal and reference value. The main difference betweenSAR and algorithmic19architectures is that a SAR converter halves thereference voltage in each cycle whileanalgorithmic converter doubles the error voltage and leavesthe reference voltage unchanged[14]. Similar to algorithmic converters, SAR converters consistof small amount of analogcircuitry to repeatedly process the data during the conversion cycle.Figure 3-2 shows thatSAR architecture only uses one reference switchfor sampling the input, one comparatorwhich is used repeatedly, and a logic network to performthe search algorithm.The power consumption of SAR is distributed in twophases: (1) charging the binaryweighted capacitors to the reference voltage during the samplingphase and (2) comparingthe input value and reference voltage during the N comparisonoperations where N is theresolution in bits. The successive approximation registerconsumes very little power relativeto the comparator because the digital logic processes one bitat a time.Vref r—ComparatorReference Switch±____Vincp —Vretij28Cj64C}2Cj6CI8C j4C j2C Ic jCo=CRS’TTTTTTTTTTSuccessive Approximation Register.GndCLK—t>And Switching Network VinVrefD7 D6 D5 D4 D3 D2 Dl DOFigure 3-2 A N-bit charge redistribution successiveapproximation architecture.Since the SAR uses digital logic to perform the search algorithm,it can be reconfigured andmodified easily. Although it is not easy to changethe implementation of the SAR ADC, thealgorithm can easily be modified when the ADC is integratedwith an on-chip20microprocessor. For example, lower resolutionsamples can be achieved by ending thesearch algorithm early. In this way, no changes willbe made to the actual circuitimplementation. Also, lower resolutionsamples can contribute to energy saving persample.Therefore, the architecture is somehow flexible.3.2 Design FlowBased on energy consideration, hardware flexibility,and feasibility of designimplementation, the successive-approximationarchitecture is chosen for this TPMSapplication. Figure 3-3 shows the systematic flow ofthe search algorithm in a SAR ADC.21The SAR presents an N-bit digital output code to the switching network,and these outputcodes can be converted back to a voltage atVInCMP by properly configuring the capacitorarray. On the other hand, the SAR, switching network,and the capacitor array form adigital-to-analog converter (DAC). The output of the DAC is continuouslyrefined using theresults of the comparator from MSB to LSB until theoutput voltage of DAC equals theinput voltage V1 or the difference is less than or equalto VLSB. The output of the ADC isFigure 3-3. Systematic flow of the search algorithm in a SARADC [13]22considered to be ready when the N-bit digital codeis a representation of the sampled inputvoltage. As the SAR ADC employs the standard binary searchin a feedback ioop, the finalN-bit digital output code will be available after theNthconversion cycle.The entire flow can be divided into two phases: sampling phaseand bit conversion phase.During the sampling phase, the input voltage issampled through the bottom plate of thecapacitor array, shown in Figure 3-4. In the meantime,VinCMP is charged to the referencevoltage of the comparator. Therefore, the total chargeon the capacitor array during thesampling phase is:Qtotai= Carray(Vref— V)=C. (Vrj7in)3-1Note that the overall capacitance of the array is21C where C is the unit capacitance.Although the total charge will be redistributed throughoutthe bit conversion phase,(neglecting leakage) it remains fixed due to the conservationof energy principle unless theentire ADC is reset for the next sample.iratorVref1Reference SwitchFigure 3-4. SAR ADC at sampling phase.23At the beginning of the bit conversion phase, thereference switch is turned off and thebottom plate of the capacitor array is connected toground. Then, the bit cycle of the SARbegins. The SAR is implemented to have an initial value startingat midscale, VreflI2.Figure 3-5 shows the SAR ADC at the most significantbit comparison cycle. The switchingnetwork corresponds to the midscale,100000002=12810 in the binary search and forces theoutput of DAC to beVrei/2. Since the off state of the reference switch leaves Vjncyfloating in the conversion phase, the voltage can change whilethe total charge on thecapacitor array remains constantas calculated in equation 3-1. The voltage atViflCMP node atthe MSB comparison cycle can be estimatedby3VInCMP = Vref—V1 3-2If the Vm is greater thanO.5Vrefl, the comparator will return a “1” to indicate the inputvoltage is greater than Vrefl/2. The result of this cycle will becarried onto the next bitapproximation by SAR. In this case, the next bit approximationwill be 110000002=19210,or if V is less than O.5Vrefl the next bit approximation will be 010000002=6410.24V Ut)Figure 3-5. SAR ADC at bit conversion phaseVrefjCo=C3paratorDue to the simplicity of the binary search algorithm, the implementationof each individualblock in SAR ADC is not as complicated. However, each individual circuitblock still playsits important role on the overall ADC performance. Therefore,the analysis on how theimplementation and performance of each individualblock affects the ADC as a wholebecomes necessary and will be presented in the following sections.3.3 Reference Switch and Switching NetworkThe switching network and the reference switch control thesampling and bit conversionstates. They can limit both the linearity and sampling speed of the ADC.The linearity isaffected by issues such as charge injection, clock feedthrough, and the“on” resistance of thereference switch. A small change in the analog signal dueto a nonideal switch can result ina voltage error at the input of the comparator. If this error is comparable toa VLSB, theoverall ADC linearity and resolution can be reduced by one bit or more. The “on”resistanceReference SwitchVrefl1VinyI I842Cj6C18C !4Cj2C jCVoltageIT T T TTI T TDoublerRS1CLSuccqssive Approxirtlation 9egister—..-——-4—-—.—— —,---—4—--—.—----ci;nci!25of the switch also determines the minimum samplingperiod of the ADC since it limitsthesettling time.As mentioned in Section 3.1, generating a separatereference voltage would increase thecomplexity, area, and power consumption of thecircuit to the extent that the referencevoltage generator might dissipate more power thanthe ADC. Choosing the supply voltageitself as the reference voltage can minimize these issues.Another advantage of using supplyvoltage as the reference is to forceVInCMP to be between O.5VDD and I .SVDD, as shown inFigure 3-6. The minimum voltage ofVflCMP is at O.5VDD, which is 0.5 V in this design.Since this voltage is greater than the threshold voltageof the comparator’s input transistor,the DC biasing circuitry at the input of the comparatorcan be eliminated for additionalpower savings.paratorFigure 3-6. Voltage range at Vincmp node of the SARADCThe linearity of the ADC depends on the fixed chargesat the VinCMP node during the bitconversion process. In order to maintain a fixed chargeat this node, the reference switchReference Switch26has to be strongly off regardless of the voltage at theVinCMP node throughout the conversionphase. When the worst case voltage ofVIICMP is at 1 .SVDD = 1.5 V, there is a chance for thesimple PMOS reference switch to have source/drain reversal. Notonly the source/drainreversal can cause circuit malfunction, but also the leakage currentcan also cause additionalpower consumption. In order to maintain a strongoff-state in the PMOS reference switch,the following equations have to be satisfied.<l’I”3-33-4“tnCMP_Vg<Vtp 3-5When Vg (the gate voltage of the PMOS reference switch)is at the voltage ofl.5Vrefl,equations 3-4 and 3-5 can be satisfied.There are several methods to reduce the effects of leakage. Oneapproach is to adjust thethreshold voltage of the PMOS switch by modifying the wellpotential. An alternativeapproach is to boost the gate voltage of the PMOS reference switchabove VDD so that theswitch will be in off-state when ADC is in the comparisonphase. For a PMOS device, thebulk terminal must be at the highest voltage to avoid reverse biasingthe diode between thep-channel transistor source and drain and its N-well. Therefore,the bulk terminal of thePMOS reference switch must be boosted too. The techniqueof voltage boosting isdescribed in Section 3.4.As mentioned earlier, using the power supply as a reference voltage offers increasedpowersavings. However, the disadvantage of this technique is a reductionin the power supply27rejection (PSR) of the ADC. As theVDD changes, Vref also changes and the ADC outputcodes change accordingly even though the inputsignal is independent of the supply voltage.In the extreme case of significant power supply drifts,the data taken at sampling phasecannot be compared because the reference voltageis constantly changing.There are two approaches to maximize the system PSR.The first method is to generate asupply independent reference voltage for the ADCat the cost of increased powerconsumption. This way the ADC samples will be independentof power supply voltagevariation. The constraint of this method is that theADC input has to be power supplyindependent; otherwise the overall PSR is still poor.Now the problem lies on the sensor.Since this TPMS application uses a MEMS sensor, the design of theADC and sensor aretightly linked. Therefore, using the supply independent reference voltagefor both the ADCand the sensor would be necessary to improve the overall sensor-ADCPSR. However, thehigher power consumption required by this method leadsus to consider other options.The second method is to make the sensor output track the supplyas well, which is theapproach used in this design [7]. Using sensors that are inherentlyratiometric with VDD(such as bridge sensors) can maximize the power supply rejectionof the sensor-ADCsystem. In this case, the MEMS sensoris a type of bridge sensor whose output changesbased on the supply voltage and resistor bridges. Although boththe ADC and the sensoritself are power supply sensitive, the overall system can be designedto be less sensitive toslow power supply variation. The advantage of this approach is thatno extra circuits areneeded to generate a power supply independent reference.283.4 Voltage DoublerDuring the sampling phase, the top plate of the capacitor ischarged to Vref through thePMOS switch and the bottom plate of the capacitor is chargedwith the input signal. At thesame time, the microcontroller sends a resetlow signal to reset the entire ADC. When theADC is in the bit conversion phase, the comparatorand SAR are implementing the bitcomparison algorithm and the PMOS switch must remain offto fix the total charge on thecapacitors. As mentioned in Section 3.3, choosingVDD as the reference voltage will causepotential source/drain reversal for the PMOS switch,but the potential circuit malfunctionscan be avoided if the gate and bulk voltages of the PMOSswitch are boosted.The normal range of operating voltages is usuallylimited in semiconductor technology;however, voltages higher than the power suppliesare required in certain applications.Switched-capacitor voltage doublers, level shifters, andcharge pumps are the most populartechniques to increase voltages, and they work by transferringcharges to a capacitive loadinvolving neither amplifiers nor regular transformers. A switched-capacitorvoltage doubler,shown in Figure 3-7, was implemented based on thecircuit reported in [20]. This voltagedoubler consists of a simple voltage booster and proper well-biasingcircuitry.29Figure 3-7. Voltage doubler with PMOS reference switchThe left half of the circuit is generating the DC wellbias voltage and storing the charges inC1 and C2 for M3 and M4 while the right half of the circuitis generating the voltage-doubledsignal through C3 and C4. The cross-coupled transistorsM1 and M2 with the capacitors Ciand C2 form the DC well bias voltage for M3 and M4 toensure no leakage occurs, and thatintrinsic diodes between the source/drain and the bulk terminalof the PMOS devices arereverse biased when the output voltage, Va, is doubled.In this design, the output voltage,Va, is targeted at 1.5VDD because increasing the voltage any higher than needed results inwasting energy. Due to the cross-coupled NMOS and capacitorC1, Vc settles to abovel.5VDD so that it can be used to boost up the N-well substrate of thePMOSwjth. When RSTis low in the sampling phase, M5 is “ON” to dischargeC4 to turn the PMOSW1th oncompletely. At the same time, C1,C2, andC3 are being charged. When RST is high duringthe conversion phase, M4 is on and Va settles to 1.5 V. With1.5 V at the gate of thePMOSjth, the device is guaranteed to remain off even ifVinCMP swings higher than VDD.30The voltage doubler circuit is relatively insensitiveto the transistor sizes used; however, theNOT gates have to be large enough to drive the capacitorC2 and C3. Also, C4 has to bedesigned large enough such that small quantitiesof charge are stored and can be used tooverdrive thePMOSjth. The waveforms of RST, Va, and Vc are shown in Figure 3-8.Transient Response— *sr --f;>.5-.25-0.0- -,__________— — —a ---•-.-- — ——2.25-2.0-1.75-1.25-1.0-7.0 25.0 50.0 75.0 100125time (ns)Figure 3-8. Transient response of the voltage doublerWhen the internal signals and output signal of voltage doubler go abovethe supply voltage,oscillatory noise like signals in the substrate can become an issue[7]. To make sure that thesignals rising aboveVDD will not cause oscillation on the power supply, a test circuit ofFigure 3-9 is used and the Fourier transform of the resultingVDD2 signal is analyzed. Fromthe discrete Fourier transform (DFT) of the signal shownin Figure 3-10, it can be seen that-----i..•.,,,---.J.1*‘-.-...__,:__•i r---:w31there is no harmonics at higher frequencies.The signal-to-noise ratio is 24.225dB (fromMatlab simulations).VDDphi (RST)‘out (Va)iclnHFigure 3-9. Circuit setup for DFT analysis32Transient ResponseTransient Response— dtt((v “fvtld2” ?resuftsflir Aibo/eoeihome/soc/grads/yir-r i’d * Pd2— phi ‘9- /outl.l, 1.25-0wr,r’r ‘r” ..w”r>1.0-.8512> -j L.25I 7&t1’10 5.0 10 15 20 0 100 200300 ‘100 500time (ns) Xl (E-3)Figure 3-10. Waveform and DFT result on Vdd2 of voltagedoubler33I I I I I I I1.061.04Vo1t . 1(V)096:*0.940.920ITI I I I I I.200 400 600 800 1000 1200 14001600 1000Thrie(jis)Figure 3-11. Voltage doubler switching time/S..:604020.;2000:5‘I.Noise0-60II.nfl0.IpiFigure 3-12. Voltage doubler FFT2pi343.5 Capacitor ArrayThe speed and linearity are the most important factorswhen the performance of an ADCisevaluated. The speed and linearity of the ADC canbe limited by the speed and linearityofthe DAC performing the charge redistribution.The DAC consists of the SAR, switchingnetwork, and the capacitor array. The SAR generatesthe 8-bit digital codes from thecomparator output, and controls the switching networkand the capacitor array to translatethe 8-bit digital code to an analog voltage atVlflcMp node. The speed of this process islimited by the settling time of the DAC, which dependson the capacitor size of eachindividual bit and the corresponding effective “on”resistance of the switches in theswitching network. The capacitor array plays a criticalrole in the ADC design because bothADC linearity and maximum sampling rate are determinedby its design.The linearity of the DAC is determined by the matchingin the capacitor array in the layoutand the nonidealities in the switching network. Assumingthe comparator and the switchingnetwork are ideal, the overall ADC linearity is determinedby the process variation of thecapacitor array and the matching error in the capacitor layout.Since the layout of thecapacitor array is the main factor of determining the desiredADC linearity, it has to be donevery carefully. Additionally, each unit capacitor hasto be designed large enough tocompensate the device matching error and makethe array insensitive to the parasiticcapacitances.35The last two paragraphs illustrate one of the trade-offsin selecting a unit capacitor size. Wewould like small capacitors to maximize thesampling rate of the converter, but largecapacitances to maximize the matching error, and thusthe linearity of the ADC.The power consumption of the ADC is also relatedto the unit capacitor size. Largercapacitors consume more energy per sample due to charging anddischarging the capacitorsin the array. As a result, there is another designtrade-off between linearity and powerconsumption. Decreasing the size of the unit capacitor allowsthe ADC to achieve fastersampling rate and lower power consumption at the costof lower linearity performance.Most circuits, especially analog circuits, dependon device matching in both active and/orpassive components. Depending on the circuit architecture, devicematching can be thedominant factor in determining the circuit performance. Unfortunately,device matchingerror is limited by manufacturing and presentin all designs and geometry dependant layouttechniques such as a common-centroid structure [21]must be used to minimize the errorassociated with mismatched devices.There are two types of random variations, peripheral and areal fluctuations,occurring duringmanufacturing the passive and active devices. Peripheral fluctuationsoccur along the edgesof the device while the areal fluctuations occur throughout thedevice. The capacitorstandard deviation matching error can be written as[211:1. I0c=7=.,jk +3-636whereka and are the areal and peripheral fluctuation constants for a capacitor.Increasing the device area increases the capacitanceand reduces the total amountof area!matching error due to the tendency forthe variations to cancel out. Increasing the deviceperiphery also decreases the total peripheral errorbecause fluctuations tend to cancel outover larger device peripheries. Therefore, based onthe properties of both peripheral andareal fluctuations, larger device sizes allow for moreprecise matching.The metal-insulator-metal (MIIVI) capacitorsare available in the 0.18 m CMOS technologyused in this work; however they cannot be used inthis application because the minimumsize of the MIM capacitor is 200 fF whichis too large for the size of the unit capacitor.Therefore, parasitic capacitances between metal platesare used in this design.When the device matching, linearity, power consumption,and speed are taken intoconsideration, the size of the unit capacitor shouldbe as small as possible while stillachieving optimal linearity and power consumption.The worse case total capacitance errorfor an 8-bit ADC occurs when every capacitor is switched,from the code transition of011111112 to 100000002 in the successive approximation register. Taking the assumptionthat ac is the Gaussian distribution of the individual capacitor error,the worst case DNL ofthe converter can be characterized by a Gaussian distributiongiven byUDNL2_1.JC2.JC3-7where N is the resolution of the ADC. To ensurethat almost all fabricated ADCs haveaworst case differential nonlinearity (DNL) error of less than1 LSB, aDNL has to be less than1/3 (i.e., 3 aDNL < 1). This will set the minimum unit capacitancevalue for the capacitor;37however, a safety margin must be included to accountfor the parasitic capacitancesassociated with routing. With all the factors considered,the unit capacitance of 15 tF ischosen for this design. The overall capacitance in thearray is approximately 3.8 pF.The capacitor is designed to have the metal plate sizeof 10.3 ,im by 10.3 m by using thetop four metal layers stacked on top of each otherand connected in parallel. The threeparasitic capacitances formed by the four metal layers addup to yield roughly 15 iF. Thisstructure is shown in Figure 3-13, where the capacitance values wereobtained from thelayout using an extraction tool. The top four metallayers were used in order to achieveminimum parasitic capacitance between the bottom plateof the unit capacitor and thesubstrate. Of course, the bottom plate of this structure hasa greater parasitic capacitancethan the top plate, so the orientation used when connecting this capacitorto the rest of thecircuit must be considered carefully.38taI8)aI5)905565W)5.04837W2.0113W]ubstrateFigure 3-13. Parasitics capacitance extractionof unit capacitorDuring the first cycle of the bit conversion phase ofADC, the voltage at theVinCMP node canbe expressed asC(inCMP=Vref+‘‘•[j_•Vt._V1nJ 3-8‘array+I*_pCMPwhere C,, is the total capacitance of thearray and CPCMP is the total parasitics capacitanceat the input of the comparator. Although this equationis derived at the first cycle of bitconversion phase, it shows that any additionalparasitic capacitances at the input of thecomparator degrade the input signal to the comparator.As a result, it affects the overallresolution of the ADC. Using the metal 6 layer as the common platefor the capacitor arraycan effectively minimize the parasitic capacitance atthe input of the comparator. Thebottom layer of the capacitor structure will be connectedto the switch network, and as long39as the switches can drive the additional parasiticcapacitance, the performance of the ADCwill suffer minimally.Adopting the common centroid layout techniqueto the capacitor array results in the schemeshown in Figure 3-14 [7].— — — — — — — — — — — —— — — — — —)u im- — — — — — — — — — — — —— — — — —[28- — — — — — — — — — — — —— — — — —64- — — — — — — — — — — —— — — — — —[2,- — — — — — — — — — — — — —— — — —64- — — — — — — — — — — —— — — — — —L2- — — — — — — — — — — —— — — — — —32- — — — — — — — — — — — —— — — — —2- — — — — — — — — —— — — —I’’T””——————— —— — —__ —[2- — — — — — — — — — — — —— — — -- — — — — — — — — — — —— — — — — -L28- — — — — — — — — — — —— — — — — -64- — — — — — — — — — — — —— — — — -L28- — — — — — — — — — — — —— — — — -64- — — — — — — — — — —— — — — — — -L2- — — — — — — — — — — —— — — — — -)u im”— — — — — — — — — — —— — — — — — —Figure 3-14. Common centroid layout for the capacitor array40In Figure 3-14, the existence of the dummy capacitor aroundthe outside of the structureensures that all capacitors in the core array have exactly thesame structures and parasiticcapacitance on each side in order cancel out any systematicmatching error.However, the floorplan shown in Figure 3-14 isnot suitable for the designed metalcapacitors due to the parasitic capacitances associated with the routing.Even using the topmetal layer for the routing paths to reduce the parasitic capacitanceto ground, thepercentage of parasitics will be greater for the smaller capacitancessince they must berouted from the center of the array. Therefore, the small capacitorsare placed on one side ofthe structure so the parasitics due to wiring are minimized. The proposedfloorplan is shownin Figure 3-15 (with the expanded view of the single unit capacitorlayout). Metal 4 andmetal 6 plates are connected to form the top plate of the unitcapacitor while metal 3 andmetal 5 plates are connected to form the bottom plate.413.6 Switching NetworkThe switching network is another component in the charge redistributionDAC which candegrade the performance of the ADC. The speed of the ADC isdetermined by the settlingtime of the charge redistribution process, which limits themaximum sampling rate of theABC. The settling time is determined by the “on” resistances ofthe switching network andthe capacitor array. Any circuit nonidealities in the switchingnetwork such as chargeinjection and clock feedthrough will degrade the linearityof the overall system. The errorcaused by those circuit nomdealities can result in a voltage errorat the VICMP node that isFigure 3-15. The proposed layout floorplan for metal plate capacitorarray.42comparable to or larger than an LSB, meaning the linearityof the ADC could be reduced byone or more bits. Consequently, some circuit techniquesmust be used to minimize thenonidealities of the switches.VrefComparatorReference Switch IvVincyrefj28C164Cj2C6C8C14C12C 1C 1CoCNetworkFigure 3-16. Simplified ADC block diagram with switching network diagram detail.In general, simple NMOS and PMOS switches consume less powerthan the CMOStransmission gates, however, a single transistor switch will have a voltage swingthat is onethreshold voltage lower than rail-to-rail. The input voltage in this applicationhas a rail-to-rail voltage swing, therefore, CMOS transmission gates must be used inorder to pass theentire signal. The constraint for CMOS transmission gates to be fully functionalis that thepower supply must be greater or equal to the sum of the NMOS and PMOSthresholdvoltages.VDDV,fl+VPEquation 3-10 sets the minimum supply voltage for the ADC. When the supplyvoltage is alittle lower than the minimum requiredVDD, the CMOS transmission gates still can be43functional; however, their resistance could be high andthe transistors may be forced tooperate in the weak inversion region which will limit the input bandwidthof the ADC.The maximum sampling rate of the ADC is determinedby the input sampling time and thespeed of the switching network. During the sampling phase, the topplates of the capacitorsin the array are charged to Vref while the bottom platesare charged to V1. Then during thebit conversion phase, the top plates of the capacitorare left floating while the bottom platesare charged to VDD or ground. In both the samplingand bit conversion phases, the MSBcapacitor, 128C, is always the maximum load to becharged. During the sampling phase, themaximum load capacitance seen by the input CMOS transmission gate switchis equal to theMSB capacitor plus the bottom plate capacitanceof other seven bit capacitors. During thebit conversion phase, each bit is switched toVDD or ground according to the output of thecomparator and the order of the SAR. Therefore, the capacitancevaries according to theconverted bit pattern. The worst case capacitance seen is at the MSBcapacitor which is halfof the total array capacitance. Assuming the small signal “on” resistanceis fixed, thesettling error can be calculated as:C)16seuling= eON3-10whereRONis the “on” resistance of the switch, C is the capacitiveloading seen by theswitch, and N is the resolution of the ADC. Assuming the ADCis ideal and there is noother source of error, the settling error must be less than 0.39 % foran ADC with 8-bitresolution. To achieve this settling error accuracy, 5.6x the timeconstants (RONC) isrequired. Usually in practice, there are many other sources of errorin the ADC so that the44resolution tends to be over designed. With 9-bit accuracy,the settling error must be lessthan 0.2% and the settling must be achieved within 6.3x thetime constant.In Table 3.-i, the “on” resistance is calculated based on the switch size usedin the switchingnetwork. With equation 3-10 and a 9-bit accuracy, the calculated settling timeis similar tothe simulated settling time. The settling time of the samplingphase is limited by the PMOSused in the reference switch rather than the transmission gates used for the inputsince it hasa higher “on” resistance. At the bit conversion phase, the settling time islimited by thePMOS switch passing VDD rather than the NMOS switch passing ground.“on” resistance1Settling Time Settling Time(6.3 RoNCworstcase)SimulationHandcalculation Hand calculationNMOS for ground 2.08 k2 25 ns 24 nsPMOS for VDD 2.5 k2 30 ns 43 nsPMOS for reference switch 4 k2 95 ns 135 nsTransmission gate for input 0.74 k2 17.43 ns 60 nsTable 3-1. Summary of switch resistance and settling time corresponds to 9-bit accurary.The data from the last column in Table 3-1 is recorded from simulation by usingtypicaldevice models. According to the simulated settling time stated in Table 3-1, theworst casein the sampling phase requires a minimum time of 135 ns for the PMOS referenceswitch toThe “on” resistance is hand-calculated based on the transistor size. NMOS and PMOS switches are2x ofminimum sized transistors. PMOS for the reference switch is 2.5x of the minimum sized transistor. NIvIOSand PMOS in the transmission gates are 4x the minimum sized transistors.45sample the input voltage properly. The PMOS switchesare the limiting factor during thebit conversion phase due to a larger “on” resistance compared to theNMOS switches.Assuming that every bit uses the same fixed amount of time, which is limitedby the largestcapacitor in the array, there are 8 cycles in the conversionphase for total time of 344 ns.Although this assumption of a fixed time is a worst-caseestimate for every bit other than theMSB, it allows for a simplified clock circuit. The minimumtime for one ADC sample isthus equal to:TADc=Tsa,,ipijng+Tconversjon= 135ns + 344ns = 479ns 3-11The maximum sampling rate can be expressed as:fADCJIX= 1= 2.09MHz 3-12TADcIt should be noted that this minimum time per sampledoes not yet include the time for the 8comparisons from the comparator that must be taken intoaccount during the bit conversionphase. The settling time may also vary significantly depending on the actualthresholdvoltage of each individual transistor, which can significantly vary the“on” resistance.Therefore, equation 3-9 must be satisfied at all times to ensure the acceptableperformanceof 1 V supply ADC even with the consideration of variationsin the threshold voltage andthe comparison time included in the total time for one ABC sample, equation3-12 showsthat the design goal of a 50 kHz sampling rate can be achieved.As mentioned earlier, another source of error from the activity of the switchingnetwork cancome from charge injection and clock feedthrough. Thistype of error usually occurs at a46transient event. Therefore, most of the switches inthe switching network such as NMOS forground and PMOS for VDD do not contribute this typeof error if they settle fast enough.The PMOS reference switch and the CMOS transmission gatesfor sampling input voltageare the possible switches contributingcharge injection error and clock feedthrough erroronto the capacitor array at the end of the samplingphase. The PMOS reference switchispurposely designed to switch off before the CMOS transmissiongate switches. TheVinCMPnode is capacitively isolated. Consequently,the charge injection from the transmission gateto the bottom plate of the capacitors becomes negligible.During the bit conversion phase,there are no switches interacting with theVinCMP node so that top plates of the capacitors arestill capacitively isolated. Therefore, the total chargeremains fixed on the top plates of thecapacitor and no charge error can be introducedonto the V1CMP node during the bitconversion phase. Although the bottom plates ofthe capacitors are charged either toVDD orground at all times during the bit conversion phase, the comparatormakes a decision onlyafter all the transient events are settled. Therefore,the effect of errors due to chargeinjection is minimal during the bit conversion phase.According to the analysis above, the PMOS reference switch isthe only switch that mayintroduce error due to charge injection and clock feedthrough toVinCMP node. Assuming thechannel charge injection is equally distributed to twosides of the switch [22], the errorvoltage on the top plate capacitor plates at the end ofthe sampling phase is calculated as:xv= WLC0x(Vgate,ref Vr VTHref)3-13ctotoJ47whereVgate,ref is the gate voltage of the PMOS reference switch, VTh,ref is the thresholdvoltage of the PMOS reference switch, andC0iis the total capacitance of the array seen atthe end of sampling phase. Assuming the overlap capacitanceis constant, the clockfeedthrough error can be expressed as:wczXV=Vov3-14gate,refuir’ i. r“‘ov ‘touilwhere C0, is the overlap capacitance perunit width. The overlap capacitance is very smallas compared withC01,therefore, the clock feedthrough error is approximately equal tozero. Using the charge injection cancellation techniques, shownin Figure 3-17, a NMOSswitch is added to the circuit so that the opposite charge packets, injectedby the PMOSreference switch and the NMOS, cancel each other [22].VinCmpFigure 3-17. One technique for reducing the cause of charge injection by addinga complementaryNMOS switch.The PMOS reference switch creates Aq1,consisting of holes whilethe NIVIOS switch createsAq2,which are electrons. To ensure Aq1 (approximately) cancelsAq2 at the end of samplingphase, the size of the NMOS switch must satisfy equation 3-15.TVgate,ref48WpLpCox(Vga:erefVrej —IVTHPI) = WWLNCOX(Vref —VTHN) 3-15As mentioned earlier, the NMOS switch does notcause charge injection only if the switchsettles fast enough. To avoid the charge injectioncaused by the NMOS switch andthePMOS switch which are used to pass ground andVDD, another technique is used to reducecharge injection and the effect of the clock feedthrough,shown in Figure 3-18 [22].DSARDSAR IIM1RovIM2GroundzxcEr ICVnCMPFigure 3-18. Another technique for reducing the cause of charge injectionand clock feedthrough.When the NMOS switch is turned off, chargeinjection phenomenon is formed by the gatechannel of M1. Assuming the total charge is equally distributedto the source and drain ofM1,zq1,can be calculated as:WLCOXDOVq1— (TH1)3-16where zq1 is half of the total charge injected by M1,andDsj is the digital signal from SAR.The charge injection cancellation technique suggestsa dummy switch can absorb thechannel charge injected from M1,which would otherwisebe deposited ontoCbt. This is truewhen Aq1 is equal to Aq2.49q2=WLC0(D—O--VTH2) 3-17When W2=O.5W1and L2=L1,then Aq1 is equal toAq2. With this dummy switch size, theeffect of clock feedthrough is suppressed. Derivationis shown in Equation 3-18 [22).W1C 2W2C—D5 +OV=0 3-18WC0, + C + 2W2C0W C0,, + C + 2W2C0,,The drawback of this technique is that the assumptionof equal splitting the charge injectedby M1 is not valid in general.3.7 ComparatorAs mentioned in earlier section, the comparison timeof the comparator determines themajor portion of the overall ADC conversion periodin which N comparisons must beprocessed completely. Yet, the comparator also determinesthe overall performance of theADC because the resolution of the comparator limits theresolution of the ADC. Due to thelow supply limitation, there is limited number of comparatorarchitectures that this designcan be used. Here, the comparator circuit is based on the circuitreported by M. Scott [3, 7],which is used to compare the voltage atVinCMP node with the reference voltage, VDD, at eachclock cycle to determine whether the previous bit signal shouldstay high or low. In Figure3-19, the comparator consists of the input NMOS differentialpair determining the inputsignal level, the cross-coupled PMOS loads,M3 and M4,forming the latch to store the result,the other PMOS devices, M1 and M2, are the switches to resetthe V0 and V0÷, nodes toVDD. The CMOS inverters are used to convert the NMOS differential output to acomparable logic output comparing with the input.When the reset signal, RST, goes off,50the V0 and V0 will go either toVDD or GND quickly depending on the input signal level.At the same time, transistors M3 and M4,form the latchto store the result, and stay in deeptriode mode. To force the transistors M3 and M4 to beout of the latch mode, the RST has tobe “on” before the next cycle comparison. Therefore,the RST signal on the schematicrefers to the clock. The voltage, Vb, is biased at 550mVby external input voltage.VOUT+Figure 3-19. Comparator Schematic.3.8 Successive Approximation RegisterThe search algorithm in the ADC is implemented in the SAR which consistsof digitalcircuits such as flip-flops which consumes lower power comparingwith other analogcircuitry. To minimize the amount of energy used in the SAR, the SAR hasto be carefullydesigned to avoid unnecessary signals switching and keep the most of signalsstatic. TheSAR in [23] is implemented with required search algorithm while keeping thesignal activity51to the minimum. In Figure 3-20, the SAR consistsof 18 digital flip-flops (DFFs) tocomplete the implementation of 8-bit ADC algorithm.Each flip-flop is implemented withstandard logic cells and only 2 out of 18 DEF are activelyswitching at one clock cycle at thebit conversion phase. The only time of the entireSAR is switching is the sampling phasebecause all DFFs are reset.Figure 3-20. 8-bit SAR schematic consists of 18 DFFs52Chapter 4Measurement ResultsThis section describes the performance ofthe ADC which is packaged and tested using acustom PCB board. Each output of the converter isbuffered on-chip to allow it to drive theinput resistance of the measurement equipment.The ADC is setup for test in Figure 4-1.Sine wave SignalADC on PCBHi:rClock generator Reset signal generator Reference voltagelVddFigure 4-1. ADC test setupThere are several metrics for characterizing the accuracyof the ADC. Most commonly usedmetrics are differential nonlinearity error, DNL, integralnonlinearity error, INL, and theeffective number of bits (ENOB).534.1 Differential and Integral NonlinearityIn an ideal ADC, it should have no offset orgain error. Therefore, those errors need to beremoved before calculating the DNL and INL. In Figure4-2, the DNL and JNL of an ADCtransfer function are defined.outputs111110101100011010001000Figure 4-2. Example of an ADC transfer function with DNL and INLThe DNL error defines the difference of the input widthof each code with the ideal inputwidth which each dotted grid width in Figure 4-2. Although eachunique ADC output codecorresponds to a certain input signal range, the outputcode width can be slightly different inVin54reality. When the output code corresponds to a large rangeof the input signal, it means thecode appears too many times comparing with other codes.This results the DNL error to bepositive. Consequently, a narrow output code indicatesa negative DNL. The DNL equationis defined as:DNL(a)= W(a)—Wideal4-1WidealThe DNL error unit is defined as an ADC LSB. If the DNL error is-1LSB, it means there isa completely missing output code. In Figure 4-3, theplot shows the DNL of the ADCdesigned. As mentioned earlier, the output offset andgain error must be removed beforecalculating the DNL and INL.Figure 4-3. Differential nonlinearity error of the ADC.55The TNt defines the error between the appearanceof a certain output code and the actualideal appearance of the output code. This is alsothe integral of the DNL errors. FromFigure 4-2, an example of bit 3 INL is labeled. TNLerror is also presented in terms of ADCLSB. Because the INL measures the integral of theoutput code errors, the magnitude of anINTL error can be greater than ILSB without havingany missing output codes.S(a) — SidealINL(a) =4-2WidealIn Figure 4-4, the INL of the designed ADCis plotted by using Matlab.Figure 4-4. Integral nonlinearity error of the ADC.564.2 Distortion Ratio and EffectiveNumber of BitsIn addition to the DNL and INL, which are usually referredto as static (low frequency)performance measures, another metric to determinethe dynamic performance of the ADC isto measure the distortion ratio by applying a sinusoidalinput signal and analyze the outputcodes in terms of frequency content. The frequencypower spectrum can later be used tocalculate the signal-to-noise and distortion ratio, SNDR, whichis the power strength and theeffective-number-of-bits, ENOB, which is the actual resolutionof the ADC. The ENOB isdefined in [14] as:ENOB=SNDR -1.766.02where the SNDR is the signal power dividedby any distortion and noise in the ADC outputwith unit in dB.In Figure 4-5, ENOB is plotted as a function of the inputfrequency at different samplingrate. It shows the best performance at ENOB of 7.09 for an inputsignal of 10kHz sampledat lOOkS/s. The sample-and-hold PMOS switch limits the maximumspeed limit of the ADCper sample due to its large settling time for passingVDD.57ENOB vs. Input Frequency8—_____________________•lOOkS/s 300kS/s —..— 500kS/s7: -‘1. I II I I‘2 \\fin(kHz)Figure 4-5. Effective number of bits, ENOB, vs input frequency,finIn Figure 4-6, ENOB is plotted versus samplingfrequency with a fixed input frequencyof10kHz.ENOB vs. Sampling frequency87654LU20- I I II I I1 1.5 2 2.5 33.5 4 4.5 5fs(1 OOkSIs)Figure 4-6. ENOB vs sampling frequency, fs584.3 Power ConsumptionPower consumption of the ADC is one of the mostimportant performance metrics in low-power ADC. Most of the power is consumed at the stageof sampling because the capacitorsare charged by both input signal and the reference voltage.In Figure 4-7, the total powerconsumption includes both the conversion powerand standby power due to leakage atdifferent sampling frequency. The higher samplingfrequency, the high power the circuitconsumes. Figure 4-7 shows measured power consumptionversus sampling frequency, fs,and the relationship is found to be linear.Power Vs. Sampling Frequency76-0a.0100k 200k 300k 400k500kSampling Frequency (SIs)Figure 4-7. Power consumption measured at differentsampling frequencies.With the measurement, the standby leakage power is lessthan lOOpW. Using the figure-ofmerit (FoM) defined as:PowerFoM = 4-42ENOBx2xf159With f1 = 10kHz with a sampling rate of lOOkS/s,a FoM of 514fJ/conversion-step isachieved. The ADC performance comparison betweenScott et al [3] and Sauerbrey et al[4], and this work is presented in Table 4-1.Sauerbrey et all [4] Scott et all [3]This workFoM 3 .48pJ/conversion step 2.63pJ/conversion step 0.5l4pJ/conversion-stepTable 4-1. Figure of merit comparison table.The SAR ADCs reported in [3, 4] having sampling frequency betweenlOOkS/s and l5OkS/swhile the power consumption ranges between0.85tW to 3OjiW with a 1V supply. Theperformance of this ADC is listed in Table 4-2.Technology TSMC 0.18gm CMOSResolution 8bitsSampling rate lOOkS/sSupply IVInput range Rail-to-RailPower consumption 1.4MW (Comparator:0.8W,Voltage Doubler: 0.6.tW)ENOB7.09 @ f=100kS/s, f=l0kHzTable 4-2. Summery of measured performance.60Chapter 5LayoutIn Figure 5-1, the location of each individual circuitblock is marked on the complete SARADC die micrograph. The overall circuit area is 0.25 ff2 Fromthis figure, it can be seenthat the majority of the ADC area is occupied by the capacitor array.The entire layout wasdone very conservatively in terms of area, especially the capacitorarray. Each unitcapacitor was spaced out by roughly 1.5X away from eachother to reduce the parasiticcapacitance between adjacent unit capacitors. The core area couldbe reduced byminimizing the capacitance spacing in the next iteration.61Quite often, the test results of a circuit may not matchwith the simulation result after thechip fabrication. There are many possibilities tocause this discrepancy such as extraparasitics, latch-ups, leakage of the device, or even device mismatch.To minimize theseproblems, layout plays an important role. Anexcellent circuit may not work afterfabrication if the layout of the circuit was done poorly.In most circuit designs, controlling the gate voltage determinesthe amount of current flowthrough the transistor. Therefore, the poiy formationof the transistor becomes extremelyFigure 5-1. Complete SAR ADC die micrograph with circuit location noted.5.1 Device Matching62important. Poly is known as a resistivematerial so a little amount of poiy differencecanmake the transistor behaviour different.The layout of the comparator used in thisADC isshown in Figure 5-2 for all the poly gatecontacts are either on the top or bottom. Duringtheprocess of the fabrication, the poiy layer isformed on the entire wafer. In order to getrid ofthe places that poiy is not needed, the technique called“etching” is used. In [24], the criticalprocess control for resist and poiy etch chamberis discussed. The dummification for polymask is also explained. At almost alltimes, all the matched devices are preferredto beplaced in the same orientation which means channeldirection of devices must be thesame.Some studies were done to examine the intrinsic statisticalfluctuations in devicecharacteristics due to different orientationof the poiy placement [25].63Figure 5-2. A comparator layoutUsually, circuit designers would like the layout to be completelysymmetrical when thecircuits are current mirror circuits or differential circuits. For currentmirror, the current isbeing copied to turn on another bias current tail of a differentialcircuit. The amount ofcurrent at current tail that needs to support the differentialcircuit can cause circuitmalfunction if the current is not properly referenced. For differentialcircuits, the matchingbetween devices is very important and can be critical. Thepoly etching process determinesthe final channel length. However, this doesn’t mean thepoly etching process would be64perfect when the devices are properly placed in thesame orientation. Placing the channel inthe same direction only can minimize the differentamount of poly being etched betweendevices. In order to match the devices better, interdigitationof the fingers between devicesis required. The metal routing is also important andcritical. In Figure 5-2, half of the layoutis placed on the left of the centre line which shows thelayout is done symmetrically on theleft and right for the metal routing and device placement.The inputs and outputs aredesigned to be dual ports and therefore theysee the same load and can be easily routed outfrom either left or right side of the block without addingextra unbalanced parasitics.5.2 Capacitor matching and necessarydummiesThe layout of the capacitor array that was discussedin Section 3.5 is shown in Figure 5-3.The unit cell capacitors placed along the perimeterof the capacitor array acts as dummycapacitors which allow the unit capacitor inside the capacitor arrayexperience the sameamount of paracitics from all its neighbors. This ensures the unitcapacitor picks up equalamount of capacitance from four side neighbors. However, the distancebetween capacitorsis far enough to make the parasitic capacitance less than 2% ofthe unit cap value. Theroutings are done carefully to avoid picking up theunnecessary parasitic capacitance alongthe route. From Figure 5-3, most of the connections aredone across the 128C unitcapacitors is because the ratio between the parasitic capacitanceassociated with the othercapacitor routing being added to the 1 28C capacitor and the 1 28Ccapacitor is negligible.65VtrIuoso Layout: Edtttng:PMUJ 8 nielodynpa;ry layout lJnntauag€l____________________1;_____1:4Ji:sraNv:cr64\ J’J’ TN N: LEEcsj [N[ C—‘kCSK’NTTh jsI19>\ — — 1R-T —— — — —— --— -+c: rS ‘‘<>:\‘S’_____________________________________________c [N_N\’\:N:64Iz rFigure 5-3. Capacitor array layout5.3 Latch-ups and guard ringsLatch-up is a failure mechanism caused by the parasitic thyristors, alsocalled as parasiticsilicon controlled rectifier, which are created by betweenMOS substrate. Once the parasiticbipolar is accidentally triggered, it allows high amount of current continuouslyflow throughit and possibly cause permanent damage to the device if the current is large.66The cause of the latch-up exists between the junctionand the bulk of the CMOS process. InFigure 5-4, the parasitic resistance between different junctionssimply forms the lateralbipolar MOSFETs, PNP and NPN, from a CMOS inverter.After re-drawing the circuitfrom the cross section, shown in Figure 5-5, the triggerpath can be seen more easily.Figure 5-4. Latch-up circuit model from a CMOS inverter cross section[26]The gate of Ml, which is the N-well tie of the p-channel MOS,should be tied to the powersupply and the gate of M2, which is the P-substrate tie ofthe n-channel MOS, should be tiedto ground. However, the lateral resistors Ri and R2 form betweenthe power supply andground if the N-well tie and P-substrate tie is not properlylaid out. As soon as the leakagecurrent being injected to the substrate, it triggers the latch-up loop.Although nowadays the vendors of CMOS IC areaware of the latch-up problems andimproved the designs and process to reduce the chance of latch-up happeningunder normalP-channel 1OS.__N—Channel MOS67usage, the CMOS designers still need to be aware ofthe issues. The good practice forpreventing latch-up happening is to put solid guard rings aroundeach circuit if possible.MlR2Figure 5-5. Latch-up circuit is re-drawn from figure 5-4.The advantage of the guard ring is minimizing the distance fromthe collector to the baseemitter region of Ml and M2; therefore, the resistanceof Ri and R2 is reduced. The crosssection of the added guard ring is shown in Figure 5-6.R68Four Guard RingsNChanneITransistorP-ChannelTransistorFigure 5-6. Guard rings prevent latch-up issues69Chapter 6ConclusionsThe design and performance measurement resultsof a 1V 8-bit ultra-low-power successiveapproximation register analog-to-digital converterare presented. The ADC is implementedin a 0.18 jim CMOS technology without using any10W-VT devices. The ADC achieves anENOB of 7.09 for a 10kHz input signal at samplingrate of lOOkS/s while consuming 1.4jiWfrom a 1V supply. The ADC is intended for use in power-constraintapplications such asmicro-sensors requiring ultra-low-power devicesdue to the limited energy and lifetimeoftheir power supply.Possible future work topics include: study ofachievable accuracy with the proposedstructure for capacitor arrays with the focus on reducingthe parasitics capacitance in thecapacitor array and the capacitor array, techniquesto improve ENOB, and techniques toimprove power consumption such as turning off thecomparator during the sampling phase[7] and decreasing the standby power of blocks.70References[1] V. Peluso, P. Vancorenland, A. M. Marques,M. S. J. Steyaert, and W. Sansen, “A900-mV Low-Power A A/D Converter with 77-dBDynamic Range,” IEEE J.Solid-State Circuits, vol. 33,pp. 1887-1897, Dec 1998.[2] T. B. Cho and P. R. Gray, “A 10 b, 20 Msample/s,35mW Pipleline A/D Converter,”IEEE J. Solid-State Circuits, vol. 30,pp. 166-172, March 1995.[3] M. Scott, B. Boser, and K. Pister, “An Ultralow-EnergyADC for Smart Dust,” iEEEJ. Solid-State Circuits, vol. 38,pp.1123-1129, July 2003.[4] J. Sauerbrey, D. Schrnitt-Landsiedel, andR. Thewes, “ A 0.5-V 1-iW SuccessiveApproximation ADC,” IEEE J.Solid-State Circuits, vol. 38,pp.1261-1265, July2003.[5] 5. Roundy, E. S. Leland, J. Baker, B. Carleton,B. Reilly, E. Lai, B. Otis, J. M.Rabaey, P. K. Wright, and V. Sundararajan, “Improvingpower output for vibration-based energy scavengers,” IEEE Pervasive Computing,vol. 4,pp.28-36, Jan-Mar.2005.[6] S. Roundy, P. Wright, and J. Rabaey, “A studyof Low Level Vibrations as a PowerSource for Wireless Sensor Nodes,” ComputerComm., vol. 26,pp.1131-1144, July2003.[7] M. Scott, “An ultra-low power ADC for distributedsensor networks,” Master ofScience Thesis, University of California at Berkeley, 2002[8] B. Razavi, Principles ofData Conversion System Design.New York: The Institute ofElectrical and Electronics Engineer, Inc., 1995.[9] B.Razavi, “Impact of Distributed Gate Resistanceon the Performance of MOSDevices,” IEEE Trans. Circuits and Systems-PartI, vol. 41,pp.750-754, November1994.[10] B.Razavi, RF Microelectronics. Taiwan: Pearson EducationTaiwan Ltd., 2003.71[11] R. J. Baker, CMOS Mixed-Signal Circuit Desgin.New Jersey: The Institute ofElectrical and Electronics Engineer, Inc., 2002.[12] J. R. Smith, Modern Communication Circuits, 2nded. New York: McGraw-Hill,1998.[13] C. B. Wang, “A 20-bit 25-kHz Delta-SigmaA/D Converter Utilizing a Frequency-Shaped Chopper Stabilization Scheme,” IEEE J. Solid-StateCircuits, vol. 36,pp.566-569, March 2001.[14] D.A. Johns and K. Martin, Analog IntegratedCircuit Design. New York: John Wileyand Sons, Inc., 1997.[15] S. K. Gupta, M. A. Inerfield, and J. Wang, “A 1-GS/s11-bit ADC with 55-dBSNDR, 250-mW Power Realized by a High Bandwidth ScalableTime-InterleavedArchitecture,” IEEE J. Solid-State Circuits, vol. 41,pp.2650-2657, Dec. 2006.[16] K. Uyttenhove and M. S. J. Steyaert, “A1.8-V 6-bit 1.3-GHz flash ADC in 0.25-/splmulm CMOS,” IEEE J. Solid-State Circuits, vol. 38,pp.1115-1122, July 2003.[17] M. P. Flynn and B. Sheahan, “A 400-Msample/s,6-b CMOS folding andinterpolating ADC,” IEEE J. Solid-State Circuits, vol. 33,pp.1932-1938.[18] H. V. D. Ploeg and R. Remmers,“A 3.3-V, 10-b, 25-MSample/s two-step ADC in0.35Lm CMOS,” IEEEJ. Solid-State Circuits, vol. 34,pp.1803-1811, Dec. 1999.[19] G. Bonfini, N. C. Guerrini, and G. Fern, “An ultralow-power switchedopamp-based10-B integrated ADC for implantable biomedical applications,” IEEETransactionson Circuits and Systems vol. 51,pp.174-177, Jan. 2004.[20] S. Basu and G.C. Temes, “Simplified clock voltagedoubler,” Electrontic Letters,Vol.35, no. 22, 28 Oct 1999,pp.1901-1902.[21] A. Hastings, The Art ofAnalog Layout, New Jersey, Prentice-Hall,Inc., 2001[22] B. Razavi, Design of AnalogCMOS Integrated Circuits. New York: McGraw-Hill,2001. 21E[23] T.O. Anderson, “Optimal Control Logic forSuccessive Approximation A-DConverters,” Computer Design, vol.11, no. 7, July 1972,pp.81-86.72[24] A.L.S. Loke, T. T. Wee, and J. R. Pfiester, “Introductionto Deep Submicron CMOSDevice Technology & Its Impact on Circuit Design,” IEEESolid-State CircuitsSociety, 8 Dec, 2004.[251 M. Hane, T. Ikezawa, and T. Ezaki, “Atomistic 3D process/device simulationconsidering gate line-edge roughness and poly-Si randomcrystal orientation effcts[MOSFET5]”, Electron Devices Meeting, 8-10 Dec 2003,pp.9.5.1-9.5.4.[26] Fairchild Semiconductor Corporation, “Understanding Latch-upin Advanced CMOSLogic,” http://www.fairchildsemi .comlan/ANIAN-600.pdf[27] E. Haseloff, Texas Instruments, “Latch-up, ESD,and other phenomena,”http://focus.ti.com/lit/anlslyaO14a/slya014a.pdf, May2000[28] D. Draxelmayr, “A 6b 600MHz 10mW ADC array in Digital9Onm CMOS,” ISSCCDig Tech Papers, Feb. 2004,pp.264-265[29] V. Peluso, P. Vancorenland, A. Marques, M.Steyaert,and W. Sansen, “A 900-mWlow-power A A/D converter with 77-dB dynamic range,” IEEEJournal of Solid-StateCircuits, vol. 33, no. 12,pp.1887-1897, Dec. 1998.


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