CMOS Bulk-Driven Mixers with Passive Baluns by Daryl Van Vorst B.A.Sc., University of British Columbia, 1998 A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF Master of Applied Science in The Faculty of Graduate Studies (Electrical and Computer Engineering) The University of British Columbia June, 2008 c© Daryl Van Vorst 2008 Abstract The design, simulation, and measurement of two bulk-driven down-conversion mixers with on- chip transformer baluns in 0.18 µm CMOS is presented. Applying either the RF signal or the local oscillator (LO) signal to the bulk connection of the transistors allows the amplification and switching stages of a conventional mixer to be combined into a single stage, thus improving the voltage headroom of the mixer. The addition of a transformer balun to the mixers improves the input impedance match, provides passive voltage gain, and performs single-ended to balanced conversion. A semi-analytical power-series analysis of the mixers is also presented. The mixer in which the RF signal is applied to the gates of the mixing transistors achieves a measured input- referred 1-dB compression point (P1dB) of −14 dBm, an input-referred third-order intercept point (IIP3) of −5.2 dBm, a gain of 13.6 dB, a noise figure (NF) of 26 dB, and an LO-to-RF isolation of 50 dB. The overall performance of both mixers is found to be comparable with other CMOS mixers, but with a higher noise figure (which can be mitigated with a high gain low-noise amplifier (LNA)). ii Table of Contents Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 The Need For Small Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 The State of the Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.4 Overview of This Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Mixer Background Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Receiver Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Mixer Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2.1 Conversion Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.2 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.3 Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.4 Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 Existing Mixer Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.1 Gilbert-Style CMOS Mixers . . . . . . . . . . . . . . . . . . . . . . . . . 13 iii Table of Contents 2.3.2 Other Mixing Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 Bulk-Driven Mixer with Integrated Transformer Balun . . . . . . . . . . . . 19 3.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 Design of the Mixing Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2.1 Resistor Values and Power Consumption . . . . . . . . . . . . . . . . . . 21 3.2.2 Transistor Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3 Monolithic Transformer Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.1 Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.2 Extraction of Equivalent Circuit Values . . . . . . . . . . . . . . . . . . . 24 3.3.3 Patterned Ground Shield . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4 Input Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.5 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.5.1 Corner Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4 Time-Varying Power Series Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1 Power Series Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.1.1 Mixer Half-Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.1.2 Power Series Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.1.3 Output Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.1.4 Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.1.5 Transistor Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.2 Numerical Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.2.1 Central Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.2.2 RF to Gate Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.2.3 RF to Bulk Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5 Performance Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.1 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.1.1 Instrumentation Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.1.2 Local Oscillator Generation . . . . . . . . . . . . . . . . . . . . . . . . . 53 iv Table of Contents 5.1.3 Dual Signal RF Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.2 Noise Figure De-embedding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.3.1 Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.3.2 Input Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.3.3 Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.4 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.5 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3.6 Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.1 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 v List of Tables 3.1 Transformer Equivalent Circuit Parameters . . . . . . . . . . . . . . . . . . . . . 27 3.2 Effect of Patterned Ground Shield at 5.8GHz . . . . . . . . . . . . . . . . . . . . 27 3.3 Corner Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1 Performance Summary and Comparison . . . . . . . . . . . . . . . . . . . . . . . 58 vi List of Figures 2.1 A Generic Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Dual Conversion Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Heterodyne Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 1 dB Compression Point (P1dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 Third-order Intercept Point (IIP3) . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.6 Cascaded Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.7 Gilbert Double-Balanced Down-Conversion BJT Mixer . . . . . . . . . . . . . . . 14 2.8 CMOS Gilbert-Style Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.9 Folded Gilbert Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.10 Capacitively Coupled Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.11 Passive CMOS Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.12 Bulk-Driven Mixer Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 Bulk-Driven Mixer with Integrated Balun (RF→Bulk) . . . . . . . . . . . . . . . 20 3.2 Bulk-Driven Mixer with Integrated Balun (RF→Gate) . . . . . . . . . . . . . . . 20 3.3 Conversion Gain vs Finger Count (N) and Finger Width (WF ) . . . . . . . . . . 22 3.4 Conversion Gain vs LO Drive Level . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5 Transformer Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.6 Transformer Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.7 Transformer Port Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.8 Effect of Series Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.9 Matching Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1 Non-linear Input-Output Representation of a Mixer . . . . . . . . . . . . . . . . . 34 vii List of Figures 4.2 Mixer Half-Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.3 DC Model Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.4 RF→Gate xi(t) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.5 RF→Gate Bias Voltage and LO Power Sweeps . . . . . . . . . . . . . . . . . . . 45 4.6 RF→Gate Conversion Gain, IIP3, and supply current vs fLO (Spectre Output) . 46 4.7 RF→Bulk xi(t) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.8 RF→Bulk Bias Voltage and LO Power Sweeps . . . . . . . . . . . . . . . . . . . 48 4.9 BSIM Model Anomaly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.10 RF→Bulk CG, IIP3, and current vs fLO (Spectre Output) . . . . . . . . . . . . . 50 5.1 Fabricated Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.2 Instrumentation Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.3 Balanced LO Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.4 RF Source Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.5 Mixer Noise De-Embedding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.6 Instrumentation Amplifier Noise Test Circuit . . . . . . . . . . . . . . . . . . . . 56 5.7 S11 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.8 S11 at RF Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.9 Non-linearity Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 viii List of Abbreviations BJT Bipolar Junction Transistor CG Conversion Gain DNW Deep N-Well CMOS Complementary Metal-Oxide-Semiconductor FCC Federal Communications Commission FoM Figure of Merit IIP3 Input-referred third-order Intercept Point ISM Industrial, Scientific and Medical LO Local Oscillator MIM Metal-Insulator-Metal capacitor MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor NF Noise Figure P1dB Input-referred 1dB compression point RF Radio Frequency RFID Radio Frequency Identification ix Acknowledgements I would like to thank my advisor, Shahriar Mirabbasi, for his helpful insight, guidance and patience. This work is funded in part by the Natural Sciences and Engineering Research Council of Canada (NSERC). CAD tool support is provided by the Canadian Microelectronics Corporation (CMC Microsystems). x Chapter 1 Introduction Recent progress in the area of radio frequency (RF) integrated circuit implementations in CMOS technology has allowed new levels of size reduction in wireless devices which have never been seen before. Many RF building blocks can now be implemented on the same die as digital components, such as processors and memories, which makes true single-chip wireless communication devices possible. In some cases, like radio-frequency identification (RFID), the entire system (not including the reader, of course) can be integrated on a die with no external components except for the antenna [14]. 1.1 The Need For Small Devices Single-chip wireless devices open up seemingly science-fiction-like possibilities such as biomedi- cal implants, complex sensor networks, implantable RFID tags, tracking devices, safety systems, surveillance, and more. Many of these devices improve quality of life, such as blood-glucose monitors and hearing aids. Without the continued size reduction that CMOS technology has afforded us, many of these applications would not be possible, or at the very least would be impractical. Implantable devices need to be small so that the host does not feel significant discomfort. Many sensors need to be small so that they can be put in tight or hard-to-reach places where important measurements need to be made, such as automotive tire pressure sensors (potentially housed in the tire stem), or chemical process monitors (where the sensor must travel with the material or liquid and not interfere with the process). Biomedical sensors, such as swallowable cameras to detect gastrointestinal problems, are also a clear example of the importance of size. 1 Chapter 1. Introduction 1.2 The State of the Art Although the implementation of on-chip RF circuits has allowed incredible size reduction for wireless devices [1], there are a few fundamental components which most wireless devices need and for which there is currently no way to implement them within a CMOS process. These include power sources (like batteries), antennas (except for very high frequencies), and accu- rate frequency references. It is possible to construct the antenna or oscillator using micro- electromechanical methods to reduce size, but this is a process that must be performed in addition to the standard CMOS fabrication process [13], thereby adding cost. The term “ac- curate” is very nebulous, and so some systems may be able to live with the frequency accuracy that can be achieved with on-chip LC, RC, or other oscillator structures. However, in the vast majority of cases, an external crystal reference is needed to provide adequate communi- cations performance and also to meet Federal Communications Commission (FCC) emission regulations. The battery is perhaps the most troublesome component for many applications. Not only can batteries easily be the largest component due to the need to store enough energy to power the device for the required time, they are also chemical devices which are sensitive to tem- perature and can be toxic. So minimizing the size of the battery, both through advances in battery technology and through reduced power consumption, is of significant interest. Power reduction is arguably of most interest because battery technology advances are relatively slow. Also, the chemical makeup of batteries is of particular concern for biomedical devices [19] or devices which may be exposed to extreme temperatures. If power consumption can be reduced enough, then alternative energy sources like vibrations, motion, or solar power could replace the battery. 1.3 Power Consumption Power consumption has a direct impact on the size of the battery. The physical size of a battery is roughly proportional to the energy which it can store. So the larger the power consumption of a device the larger the battery must be, assuming the battery life target remains constant. For this reason, power reduction is a critical issue in many wireless applications, particularly 2 Chapter 1. Introduction sensors and portable devices. The average power consumption of a communications device is not trivial to determine. The sum of the power consumption of all of the individual components does not provide the average power because some or many of them are only on when they need to be on. Many factors affect the average power consumption, including the protocol which is implemented, the usage scenario for the device, the signal conditions (such as interference causing additional re- transmissions), and even temperature. Reducing the power consumption of every circuit in the device would clearly reduce the average power consumption, but due to the complex operation of the device, certain circuits will have a much larger impact on the average power consumption than other circuits. One part of the design which can have a large effect on average power is the radio receiver and demodulator. In many applications, this part of the system must wake up periodically to detect the presence of an incoming signal. Depending on many system factors (particularly the chosen protocol and clock accuracy), the amount of time that the receiver stays on can vary widely and in some cases dominate the average power consumption. This is particularly true for asynchronous applications where the battery powered device must do something “on demand”. As a result, minimizing the power consumption of the receiver front-end is often an important design goal. Power consumption alone is not the only thing which dictates the size of the battery or affects the potential use of alternative power sources. The supply voltage necessary to support proper operation of the circuit can also have a direct impact. For example, a high operating voltage requires multiple cells to operate. Energy harvesting methods may not be capable of providing high supply voltages. Along with the power consumption, reducing the supply voltage is therefore also a useful task to undertake. 1.4 Overview of This Work There are a few potentially power hungry circuits in a transceiver front-end, such as local oscillators and phase-locked loop frequency synthesizers, low-noise amplifiers, power amplifiers, and mixers. Mixers, in particular body-effect mixers, are the topic of this thesis. Exploiting 3 Chapter 1. Introduction body-effect is a potential way to reduce the operating voltage requirement (and thereby also the power consumption) of the mixer. In this work the performance of two body-effect mixers with on-chip transformer baluns is explored. The transformer balun is an addition to previous bulk-driven mixer designs which increases the conversion gain of the mixer, provides a good input impedance match, and provides single-ended to balanced conversion. The contributions of this work are the design, simulation, and measurement of the two bulk-driven mixers. The simulation includes a semi-analytical power-series analysis of the mixer core. As the analysis neglects parasitic effects (such as capacitance), it is only valid at relatively low frequencies. However, it provides some insight into the operation of the mixer core. Introductory background material on mixers and radio transceivers in general is presented in Chapter 2. In Chapter 3, the two bulk-driven topologies with integrated transformer baluns are presented along with some simulation results. The power series analysis is presented in Chapter 4. Finally, the performance measurement of the mixers is presented in Chapter 5. Overall, the mixers perform well compared (by means of a figure of merit) to other mixer topologies, but suffer from relatively high noise figure. The noise figure, however, can be mitigated with the use of a higher-gain LNA in the receive path. The mixers also have relatively good linearity considering their gain and power consumption, which reduces the linearity issues that are involved with increasing the gain of the LNA. 4 Chapter 2 Mixer Background Information Mixers are most commonly used in RF circuits to achieve frequency translation, but can also be used as phase detectors in PLLs [6], as variable gain amplifiers [10], and as frequency discriminators in FM (frequency modulation) receivers [20]. An ideal mixer is a multiplier. That is, the output voltage (or current) is the product of two input signal voltages (or currents), as illustrated in Figure 2.1. If one of the two input signals is a sinusoid (referred to as the local oscillator or LO), then the spectrum of the other signal is shifted in frequency as a result of time-domain multiplication. This can be illustrated by use of the frequency convolution property of the Fourier transform, which, for the case that f2(t) = cos(ω0t), results in [36, p. 108] y(t) = f1(t) cos(ω0t) F ⇒ Y (ω) = 1 2pi F (ω) ∗ pi [δ(ω + ω0) + δ(ω + ω0)] Y (ω) = 1 2 [F (ω + ω0) + F (ω − ω0)] , (2.1) where the ∗ denotes convolution and F (ω) and Y (ω) are, respectively, the Fourier transforms of the input and output signals. y(t) f2(t) f1(t) Figure 2.1: A Generic Mixer 5 Chapter 2. Mixer Background Information 2.1 Receiver Architectures Presented here is some very general information about receiver architectures. It is intended to provide an idea of how mixers are commonly used in radio receivers. Similar concepts and usages apply to radio transmitters. Until very recently, most radio receivers employed a heterodyne architecture [4] similar to what is shown in Figure 2.2. The heterodyne structure involves mixing the received signal with a local oscillator signal at a different frequency to produce an IF signal which is then filtered with a band-pass filter. Multiple frequency translations can exist in such receivers. In this architecture the first intermediate frequency (IF) filter and second LO (LO2 in the figure) are usually fixed frequency. Also, the first IF filter frequency is selected at a moderately high frequency to increase the spacing between the image frequency and the desired signal. The higher frequency separation between the fundamental (the desired signal) and the image signal significantly reduces the requirements of the image reject filter. The fixed intermediate frequency allows the designer to use a fixed-frequency channel select filter, which can be made to have significantly better characteristics than adjustable ones. A downside to the heterodyne architecture is the need for high-quality filters at RF and IF frequencies for image rejection and channel selection. Such filters are usually either surface acoustic wave filters, ceramic filters, crystal filters, or cavity filters. All of those devices occupy relatively large circuit board areas when compared to other RF building blocks. They also cannot generally be implemented in a monolithic design. LO1 (Variable) First IF Filter Second IF Filter LO2 (Fixed) Image FilterLNA Demodulator Figure 2.2: Dual Conversion Receiver These limitations along with progress in the area of complex RF integrated circuits (partic- ularly CMOS ones), has led to the use of direct-conversion receivers or low-IF receivers receivers 6 Chapter 2. Mixer Background Information LO LNA Demodulator 0◦ 90◦ Figure 2.3: Heterodyne Receiver (Figure 2.3). In these receivers, there is only one frequency conversion. In the direct-conversion receiver, where the IF frequency is DC, the image frequency can be considered to be at the same frequency as the desired signal, and so is not filtered out before the mixer. For low-IF receivers, the image frequency exists, but more complex mixing structures (image reject mixers) can be used to remove it. In addition, the low IF frequency of these receivers allows the channel selection to be done either with a high-Q low-pass analog filter, or digitally using digital signal processing. As is likely apparent from the preceding discussion, mixers play a key role in virtually every RF transceiver. They must reliably multiply their two input signals without corrupting them, and in the case of a receiver, they must often do this while supporting an enormous dynamic range of input signal strength (potentially spanning many 10’s of dB). Clearly the performance of the mixer can have a significant impact on the overall radio performance (both for transmit and receive), and so it must be accurately characterised. The most common performance metrics which are commonly used to describe the behaviour of mixers are discussed in the following section. 2.2 Mixer Performance Metrics Real mixers depart from the idealized case in a number respects, but the primary issues are linearity and noise. An additional issue is leakage between the mixer ports (such as LO→RF or RF→LO). Also, the gain of a mixer is in general not unity. The way these aspects of a mixer are commonly characterized is described below. 7 Chapter 2. Mixer Background Information 2.2.1 Conversion Gain The conversion gain of a mixer is usually expressed in dB, and is defined as G = Pout Pin , (2.2) where Pout is the power of the desired signal at the output of the mixer, and Pin is the power of the input signal. In CMOS devices, the conversion gain is often measured in terms of voltage gain instead of power gain because of the lack of a precisely defined characteristic impedance. In that case, the conversion gain becomes Gv = V 2out V 2in , (2.3) where Vout is the magnitude of the desired output signal and Vin is the magnitude of the input signal. If the input and output impedances of the mixer are the same then G = Gv. The gain of a mixer is always measured with a low enough input signal level so that any non-linear effects are negligible. 2.2.2 Linearity The linearity of a mixer is most commonly characterised by its input-referred 1 dB compression point (P1dB) and by its third-order input intercept point (IIP3). P1dB is the input power level where the output signal level drops by 1 dB from the ideal linear case (illustrated in Figure 2.4). IIP3 is the input signal level where the extrapolated 3rd-order intermodulation product is equal to the ideal linear (fundamental) signal level, both at the output (illustrated in Figure 2.5). The IIP3 measurement is done with two input signals which are closely spaced (at frequencies ω1 and ω2). The third-order nonlinearity produces intermodulation products at 2ω1 − ω2 and 2ω2−ω1 among other frequencies, but these are of the most interest because of the proximity to the desired signal. IIP3 performance is of particular concern in many wireless applications where there are many equally spaced channels because the third-order product from two adjacent channels lands on the next channel over (above and below the two channels), as predicted by the above expressions. Generally, the power of the resulting products is very low compared to 8 Chapter 2. Mixer Background Information the power of the signals which produce them, so they are of little consequence to those signals. However, they are a major problem if the neighbouring channel (where the spectrum of the third-order product lands) is very weak and it is to be received. The IIP3 products arise from non-linearities in stages before the first channel-select filter in the receiver (“First IF Filter” in Figure 2.2), so they cannot be filtered out because the source of the products are signals that are in the pass-band of the image reject and preselection filters (a preselection filter is not indicated in Figure 2.2, but would be before the LNA if it is implemented). As a result, careful attention must be paid when designing a receiver to ensure that the overall IIP3 performance of the receiver’s front end is adequate to handle the most extreme cases of multiple high-power adjacent channels which are likely to appear in normal operation. IIP3 is of particular concern for mixers because they are usually situated after the LNA, and so are subjected to substantially stronger signals than the LNA. The third-order products, as will be seen below and is depicted in Figure 2.5, rise exponentially relative to the power of the signals which produce them. The ones produced within the first mixer are usually what define the receiver’s overall IIP3 performance. The intermodulation issue described above is common for frequency-division multiplexing systems, but it is not the only potential linearity related problem. Other issues include spectral regrowth caused by intermodulation in the transmit path, and compression or distortion of the desired signal in the receive path. It is worth exploring the non-linear performance a little further, both for some relevant insight into this discussion and as background information for the time varying power series analysis in Chapter 4. By substituting two tones vi(t) = A1 cos(ω1t) +A2 cos(ω2t) (2.4) into the “loose”1 Taylor series expansion of the mixer transfer function vo(t) = k1vi(t) + k2v 2 i (t) + k3v 3 i (t) + . . . , (2.5) 1This is referred to as “loose” because the input and output variables refer to different frequency bands. An example of this use can be found in [39]. 9 Chapter 2. Mixer Background Information Linear Extrapolation 1dB Actual Output P1dB P o u t (d B ) Pin (dB) Figure 2.4: 1 dB Compression Point (P1dB) the resulting products are: (following [35, p. 93], but with a correction made to the magnitude of some of the second order terms): vo(t) = k1 (A1 cos(ω1t) +A2 cos(ω2t)) + k2 [ A21 1 + cos(2ω1t) 2 +A22 1 + cos(2ω2t) 2 + A1A2 ( cos((ω1 + ω2)t) + cos((ω1 − ω2)t) )] + k3 {[ A31 ( 3 cos(ω1t) 4 + cos(3ω1t) 4 ) + A32 ( 3 cos(ω2t) 4 + cos(3ω2t) 4 )] + A21A2 [ 3 2 cos(ω2t) + 3 4 cos((2ω1 + ω2)t) + 3 4 cos((2ω1 − ω2)t) ] +A2A 2 1 [ 3 2 cos(ω1t) + 3 4 cos((2ω2 + ω1)t) + 3 4 cos((2ω2 − ω1)t) ]} + · · · (2.6) Two-tone intermodulation tests are typically done with input signals of equal amplitude, resulting in A1 = A2 = A. With this, the input signal level at which the linear and 3rd-order terms are equal (illustrated in Figure 2.5), is given by A2IIP3 = ∣∣∣∣4k13k3 ∣∣∣∣ , (2.7) 10 Chapter 2. Mixer Background Information IIP3 Extrapolated 3rd Order Product (3dB/1dB Slope) Extrapolated Fundamental P o u t (d B ) Pin (dB) Figure 2.5: Third-order Intercept Point (IIP3) where AIIP3 is the input signal amplitude. Inspecting (2.6), it is seen that there are two terms which influence the fundamental fre- quencies: the linear term (involving k1), and a third-order term (involving k3). The input signal level at which the linear term is 1 dB higher than the total output power at the fundamental (while ignoring terms higher than 3rd order, and setting A2 = 0) can be expressed as A2P1dB = ∣∣∣∣4k13k3 ( 10− 1 20 − 1 )∣∣∣∣ (2.8) which differs from (2.7) by a factor of 10−1/20 − 1 or equivalently −9.6 dB. So, as long as linearities higher than third-order are not dominant, the input referred 1 dB compression point will be 9.6 dB lower than input-referred third-order intercept point. 2.2.3 Noise Figure Noise figure is a measure of how much noise a circuit adds to an input signal [35, pp. 77-81]. In wireless communication systems the received signal is often very weak (potentially very close to the thermal noise floor), so the noise performance of a receiver is of paramount importance. Noise figure, NF , is generally taken as the noise factor, F , expressed in decibels: NF = 10 log(F ) (2.9) 11 Chapter 2. Mixer Background Information However, F is also sometimes called noise figure. The noise factor for a device is F = Si/Si So/No , (2.10) where Si/Ni and So/No are, respectively, the input and output signal to noise ratios (SNR) in the band of interest. An ideal noiseless device has a noise factor of 1 (or equivalently a noise figure of 0 dB). The noise factor of a cascaded series of stages (Figure 2.6) can be expressed by F = F1 + F2 − 1 G1 + F3 − 1 G1G2 + · · ·+ Fn − 1 G1G2 · · ·Gn−1 , (2.11) where Fn is the noise factor of the n-th stage, and Gn is the gain of the n-th stage. G1, F1 G2, F2 Si Ni Gn, Fn So No Figure 2.6: Cascaded Noise Figure These noise factor expressions apply to any RF building block. However, where there is a frequency conversion, such as in a mixer, the frequency bands of the input and output SNRs are different. 2.2.4 Isolation A mixer is a three port device and as previously mentioned is ideally a multiplier which takes two inputs and provides one output. In the ideal case there is no power flow from one of the inputs to the other input, and also no power flow from either input directly to the output (i.e. without undergoing multiplication). In a real mixer the ports are not completely isolated and signal entering one input can leak to the other input or the output. In this work isolation is defined as the ratio of signal power exiting a port relative to the power (of the same signal) applied to another port. For example, the LO to RF isolation is LO to RF isolation = PLO at the RF port PLO , (2.12) 12 Chapter 2. Mixer Background Information where PLO at the RF port is the power exiting the RF port when the applied LO power is PLO. Ideally this ratio would be 0 or −∞ dB. Poor isolation is in general a significant problem in system-on-chip designs because of the extreme proximity of the components and the relatively low resistivity of the substrate (when compared to typical circuit board properties). In relation to mixers, a detrimental effect that poor isolation can have is the production of a DC offset at the mixer output resulting from the self-mixing of the LO signal (or RF signal) when it finds its way into the RF (or LO) input. 2.3 Existing Mixer Topologies In this chapter a number of common mixer topologies which are appropriate for implementation in monolithic systems (particularly CMOS integrated circuits) are discussed. 2.3.1 Gilbert-Style CMOS Mixers The most common mixer found in RF circuits today is the so-called “Gilbert mixer”, coined after Barrie Gilbert’s 1968 paper [17] describing a BJT transistor multiplier (shown adapted for use as a mixer in Figure 2.7). 2 The illustrated mixer uses NPN transistors (it is possible to flip the structure upside-down and use PNP transistors), and only the core of Gilbter’s multiplier structure is used. In Gilbert’s design additional circuitry exists for improved linearity. The illustrated mixer is configured as a down-conversion mixer (it takes an RF signal as an input and produces a lower-frequency IF signal). The RF and IF connections can be interchanged for use as an up-conversion mixer, but in this case the resistive loads are often replaced with parallel inductor-capacitor tank circuits to improve the high frequency gain. The mixer shown is referred to as “double-balanced” because both the RF and LO inputs are balanced (differential). Due to the symmetry of the double-balanced structure, even-order non- linearities are cancelled when the output is also taken differentially. Even-order non-linearities cause both negative or positive signal excursions of equal magnitude at the input to produce the same excursion at the output. That is, the sign of the excursion at the input does not affect 2It is interesting to note that the basic multiplying structure did not originate there and can be found in previous articles and patents, such as [28] and [22]. Credit is owed to James Long for pointing this out (http://www.analog-rf.com/1ndex.shtml). 13 Chapter 2. Mixer Background Information the output. So as long as the input signal is balanced, each single-ended output will be affected the same way so the net differential effect at the output is null. This is, of course, only true if everything is exactly symmetrical. Mixers of this style are usually driven with a strong enough LO signal to cause the upper set of four transistors to act as switches, effectively multiplying the RF (or IF) signal by a square wave instead of by a sinusoid. The additional products that result from mixing with the harmonics of the square wave are usually of high enough frequency that they are either naturally filtered out by the low-pass nature of the circuit (due to parasitic capacitors), or can be filtered out with the addition of low-pass filters. Similarly, signals that could be picked up by the antenna of the receiver and could potentially be down-mixed by the harmonics to the IF frequency are far enough away from the desired signal that they can be filtered out by the pre-selection or image-reject filters. IFout+ − + − LOin RFin+ RFin− Figure 2.7: Gilbert Double-Balanced Down-Conversion BJT Mixer The BJT mixer can be directly converted for use in CMOS technologies simply by substi- tuting n-channel MOSFETs for all of the NPN BJTs. The resulting CMOS implementation is shown in Figure 2.8. Again, the LO signal is usually large enough to cause the top four transistors to act as switches. Like the BJT mixer, this mixer can be used for either up- or down-conversion by interchanging the RF and IF connections. Although the CMOS Gilbert mixer lends itself well to implementation in digital CMOS technology, a drawback is the required supply voltage and the associated power consumption. As indicated in Figure 2.8, the mixer is comprised of three levels of transistors stacked one on 14 Chapter 2. Mixer Background Information RFin Vbias } Switching Stage } Gain StageLOin IFout } Bias + − + − − + Figure 2.8: CMOS Gilbert-Style Mixer top of another. This stacked arrangement consumes supply headroom and sets a lower limit on the supply voltage. For many applications this may not be a severe limitation [37], but for ultra-low-voltage or ultra-low-power applications alternative structures are worth investigating. 2.3.2 Other Mixing Structures Folded Mixers Folding is a commonly used technique to reduce the supply voltage requirements of analog circuits. To fold a circuit, a transistor which was originally stacked on top of another one (such as the common-gate stage in a cascode amplifier) is changed from n-channel to p-channel (or vice-versa) and placed beside the bottom transistor thereby reducing the supply requirements. In a Gilbert mixer, the entire switching stage (consisting of four transistors) can be folded in an analogous way, as shown in Figure 2.9. A downside to folding is that twice the original supply current is required because the bias current for the two stages is no longer reused (this is mitigated somewhat by a reduction in supply voltage). Additional circuitry is also required to provide biasing for the folded node while presenting it with a high impedance, such as a current source or LC tank circuit. An example of a CMOS implementation of a folded mixer is [34]. 15 Chapter 2. Mixer Background Information RFin Vbias + − + LOin − IFout+ − Figure 2.9: Folded Gilbert Mixer Capacitively and Inductively Coupled Mixers Alternative methods of folding involve the use of capacitors or transformers for coupling the two stages together. This allows one to continue to use the same type of MOSFET (n-channel or p-channel) as in the original circuit by allowing a shift in bias voltage. A capacitively coupled folded mixer is presented in [43], and transformer coupled mixers are presented in [27] and [9]. An example of a capacitively coupled mixer is shown in Figure 2.10. RFin Vbias + − IFout+ − + − LOin Figure 2.10: Capacitively Coupled Mixer Passive Mixers Passive mixers accomplish mixing through the use of transistor switches. There are no active gain stages in passive mixers. The switching transistor portion of a Gilbert style CMOS mixer without the amplification stage is essentially a passive mixer. An example passive mixer is 16 Chapter 2. Mixer Background Information illustrated in Figure 2.11. RF+ LO+ IF + − RF− LO+ LO− LO− Figure 2.11: Passive CMOS Mixer Passive mixers offer higher linearity than the other mixing structures discussed here [16, 18, 44]. This arises from the use of large transistors to better approximate ideal switches, and the lack of an amplification stage. A downside to passive mixers is that they have conversion loss and the large transistors may demand higher drive capability from the LO. Bulk-Driven Mixer Topologies Relatively new structures for CMOS mixers are bulk-driven topologies. In a bulk-driven mixer the bulk connection of the MOSFETs is used as another input instead of being tied to one of the supply rails or to the source. These mixers use the non-linear characteristics of the body- effect to accomplish mixing. The body-effect refers to a change in the threshold voltage of the transistor, Vth, due to a difference in potential between the source and bulk connections. The long-channel approximation of the body-effect is expressed as [33, p. 258] Vth = Vth0 + γ [√ 2φf + VSB − √ 2φf ] , (2.13) where VSB is the source-bulk voltage, Vth0 is the nominal threshold voltage when VSB = 0, γ is a technology parameter, and 2φf is the surface potential. Additional terms are added in the BSIM models (e.g., BSIM3v3 [7]) to account for short-channel effects. From a functionality point of view, the body effect can be thought of in two ways. It either provides control over the threshold voltage, or it provides a small-signal gain path for signals applied to the bulk. Both of these effects can be exploited to combine the gain and switching 17 Chapter 2. Mixer Background Information stages of the conventional mixer (Figure 2.8) into a single stage, as illustrated in Figure 2.12. The dual use of the bulk (as either the LO input or the RF input) is also indicated in the figure. One main benefit of using this structure is a reduction in the required supply voltage by reducing the number of transistors which are stacked on top of each other within the mixer. IFout+ − + − + − Gate Drive (RF or LO) Bulk Drive (RF or LO) Vbias } Optional Tail Current Source Figure 2.12: Bulk-Driven Mixer Core Most bulk-driven mixers to date, [12, 21, 23, 24, 42], essentially use the topology shown in Figure 2.12. In [42] the core transistors are PMOS and it is a single-balanced mixer (rather than the double-balanced NMOS version shown here), and it has active loads. As indicated in the diagram, the current tail is considered optional and is not used in [24, 42] and [23]. The bulk-driven mixers in [5, 38] use an active load concept. In these mixers the RF signal is applied to a standard differential pair (without the current tail) with PMOS current-source loads. The LO signal is applied to the bulk connection of the active loads and a common-mode feedback loop drives the gates of the active loads. The connection of the LO to the active loads modulates them and results in a multiplication of the RF signal by the LO signal. 18 Chapter 3 Bulk-Driven Mixer with Integrated Transformer Balun The topology of this mixer addresses the continuing trend of supply voltage reduction that results in lower voltage headroom (since the corresponding reduction in transistor threshold voltage levels is lower). Previous bulk-mixer cores also addressed such concerns, but suffer from low gain. The addition of a transformer balun in this mixer increases the gain of the mixer, and can also provide an excellent input impedance match. The input match is desirable if this mixer is to be used as a first mixer in a dual-conversion receiver, where an off-chip image-reject filter usually precedes it. Two papers, by the author of this thesis, discussing this mixer have been published to date: [40, 41]. The first paper, [40], focuses on the design and simulation of the mixer, while the second paper, [41], highlights the measurement results. 3.1 Structure Two mixers with similar structure, but different RF signal flow, have been designed. In one of the mixers, the RF signal is applied to the bulk and the local oscillator is applied to the gates. This mixer is referred to as the RF→Bulk case and is illustrated in Figure 3.1. In the other mixer, the RF signal is applied to the gates (Figure 3.2) and is referred to as the RF→Gate case. These two structures were chosen to compare the relative merits of applying the RF signal to the bulk versus the gates. At least one previous author, [23], has applied the RF signal to the bulk while most have applied RF to the gates. The primary motivation for applying RF to the gates is to achieve higher gain by using the gate transconductance which is much higher 19 Chapter 3. Bulk-Driven Mixer with Integrated Transformer Balun LOin IFout RFin + − +− VCT Figure 3.1: Bulk-Driven Mixer with Integrated Balun (RF→Bulk) LOin IFout RFin + − +− VCT Figure 3.2: Bulk-Driven Mixer with Integrated Balun (RF→Gate) than the bulk transconductance. 3.2 Design of the Mixing Core The design procedure for the mixing core involves finding appropriate transistor sizes, bias levels, resistor values, and LO drive level. It is a balanced structure, so all of the transistor sizes are the same as well as the two resistors. The mixer is designed for the 5.8 GHz ISM (industrial, scientific, and medical) band, and power consumption and gain are assumed to be the important parameters to be optimized for. 20 Chapter 3. Bulk-Driven Mixer with Integrated Transformer Balun 3.2.1 Resistor Values and Power Consumption Finding appropriate resistor values involves making a tradeoff between power consumption, gain, and output impedance. Output impedance is of significant importance for this mixer because the output is brought off chip for measurement in the lab. This makes stray capacitance a potential problem because of bandwidth limitation. With this in mind, an output impedance of 1 kΩ is chosen to allow an output bandwidth of 160 MHz assuming a stray capacitance of 1 pF. Low-cost 200 MHz oscilloscope probes have an input capacitance 3 on the order of 10 pF, which would limit the output bandwidth to 16 MHz. One of the goals of the design is to demonstrate its potential for use in low-voltage circuits or in technologies whose supply voltage has been scaled down relative to transistor threshold voltages more than what is seen in current processes. To this end, a supply voltage of 1 V is chosen in a 0.18 µm CMOS technology whose typical supply is 1.8 V. Doing so, in combination with the selection of 1 kΩ load resistors, fixes the total target current consumption at 1 mA if the DC bias level of the output is set midway between VDD and VSS to (approximately) maximize the output signal swing. 3.2.2 Transistor Sizing To determine the size of the transistors, the conversion gain of the mixer core was simulated using Cadence Spectre for a range of transistor sizes, and the results are shown in Figure 3.3. Based on this data, a transistor size of WF = 5 µm and N = 7 was chosen. It is arguable that this is not the optimal transistor size, but it was chosen on the basis that minimizing the transistor size both reduces the overall layout size, and would also reduce the capacitive load presented to the LO thus potentially reducing the LO drive requirement. The figure shows that little improvement is to be expected to very wide transistors or large finger counts. It was found that the conversion gain is not strongly dependent on the LO drive level and good performance for both RF→Bulk and RF→Gate topologies was achieved at a level of 2 dBm, as indicated in Figure 3.4. Another reason that 2 dBm is chosen is that the resulting peak-to-peak voltage is slightly less than 1 V, thus keeping the level to a realizable level for an on-chip LO. 3See, for example, probes at Tektronix (http://www.tek.com/products/accessories/oscilloscope probes/passive.html). 21 Chapter 3. Bulk-Driven Mixer with Integrated Transformer Balun -30 -25 -20 -15 -10 -5 0 5 10 15 2 4 6 8 10 12 14 16 18 20 WF = 2 µm WF = 4 µm WF = 6 µm WF = 8 µm RF→Gate RF→Bulk Fingers (N) C on v er si on G ai n (d B V ) Figure 3.3: Conversion Gain vs Finger Count (N) and Finger Width (WF ) -30 -25 -20 -15 -10 -5 0 5 10 15 -4 -2 0 2 4 RF→Gate RF→Bulk PLO (dBm) C on v er si on G ai n (d B ) Figure 3.4: Conversion Gain vs LO Drive Level During the design phase there was some uncertainty as to the accuracy of modelling of the bulk behaviour. It is unlikely that the foundry has precisely modelled the bulk in such a way that it is accurate for use in a topology where the bulk is very deliberately put in the signal path. Most RF circuits do not use the body effect in this way. So a width was chosen at a point on the graph where there is little deviation in performance for a change in N or WF . These transistor dimensions also facilitate a square layout, which aids in creating an over- all symmetric layout. In balanced mixers like this, an overall symmetric layout is essential to achieve good LO→RF isolation, good gain and phase matching, and good second-order distor- tion rejection. 22 Chapter 3. Bulk-Driven Mixer with Integrated Transformer Balun 3.3 Monolithic Transformer Balun There are various potential transformer layouts for use in CMOS RF circuits [15, 26, 45]. The design rules for the chosen technology limit the potential transformer layouts to some degree. To adhere to the design rules and maximize the self-resonant frequency of the transformer, an Frlan style [15] layout was chosen. The thick top metal option that is available for the TSMC 0.18µm process was chosen to minimize winding resistance. Several transformer layouts were simulated in ADS Momentum to find a design which has good coupling and minimal loss. To model the transformer in Momentum, the substrate, oxide layers, and all used metal layers were modelled based on the data provided by the foundry. The iterations included changes to trace widths and spacings, overall dimension, and minor layout alterations. The size and structure shown in Figure 3.5 was eventually settled on. The outside dimension of the transformer (not including guard space), was limited to 200µm to keep the chip area low. The traces are all 6 µm with a spacing of 1.5 µm. 200µm 200µm Figure 3.5: Transformer Layout 3.3.1 Equivalent Circuit A simplified equivalent circuit of the transformer is shown in Figure 3.6 [26] (the centre tap is omitted). This is only one possible model. The placement of the leakage inductance, Ll, and the magnetizing inductance, Lm, are somewhat arbitrary, as discussed in [26] and [30, pp. 535-538]. 23 Chapter 3. Bulk-Driven Mixer with Integrated Transformer Balun RP Lm = k 2LP Ll = (1− k 2)LP RS + − VoVi + − 1 : n k Ideal Figure 3.6: Transformer Equivalent Circuit Corresponding to this model, the coupling coefficient, k, is related to the mutual inductance, M , of the two coils by M = k √ LPLS , (3.1) where LP and LS are the primary and secondary winding inductances, respectively. The turns ratio is given by n = √ LS LP . (3.2) The model in Figure 3.6 neglects capacitive effects and substrate loss, so its validity is limited to frequencies well below the self-resonant frequency of the transformer. It should be noted that its use in this work is only for approximation and illustrative purposes. All circuit simulations are performed using multi-port s-parameter models. 3.3.2 Extraction of Circuit Values from Scattering Parameters Although extracted parameters are not used in the simulation, they illustrate the transformer’s general characteristics. Extracting the parameters also provides a simple mechanism to verify that the RF simulation software is producing sensible simulation results. The standard format for RF measurement results are scattering parameters (s-parameters). Scattering parameters relate the relative magnitudes of the forward and reverse travelling waves between all ports of a circuit [31, pp. 539-541]. The output provided by the ADS Momentum simulator are s-parameters. To extract approximate lumped element values to fit our transformer model (Figure 3.6), it is easier to work in terms of impedance parameters (Z-parameters). Z-parameters relate the 24 Chapter 3. Bulk-Driven Mixer with Integrated Transformer Balun voltage and current at each terminal of a multi-port network by [31, pp. 530-539] [V ] = [Z][I], (3.3) where the vector [V ] contains the voltages at each port and the vector [I] contains the currents entering each port, and [Z] is the impedance matrix. The s-parameters provided by Momentum are converted to z-parameters using the mathematical tools available within ADS. The transformer illustrated in Figure 3.5 has a total of 6 electrical connections (ports): One for each of the two connections to the primary winding, three for the secondary winding and its centre tap, and lastly for the ground ring. The port numbering is illustrated in Figure 3.7. Ground Ring 1 3 2 5 4 6 Figure 3.7: Transformer Port Numbering To extract the resistance and inductance of the primary winding, the voltage at ports 1 and 3 is calculated from the impedance matrix for a 1A test current by V1 V2 V3 V4 V5 V6 = Z11 · · · Z16 ... . . . ... Z61 · · · Z66 1 0 −1 0 0 0 . (3.4) 25 Chapter 3. Bulk-Driven Mixer with Integrated Transformer Balun From the voltages, the resistance and inductance can be calculated as R = ℜ{V1 − V3} 1A , and (3.5) L = ℑ{V1 − V3} 2pif · 1A . (3.6) A similar calculation can be performed to find the inductance and resistance of the secondary winding (leaving the centre tap open). Once both the primary and secondary winding induc- tances are known, the turns ratio can be calculated using (3.2). The mutual inductance,M , relates the voltage on one coil (which is open circuited and thus has no current flowing through it) to the current in the other coil. This is expressed by VS =M dIP dt + LS dIS dt , or (3.7) VP =M dIS dt + LP dIP dt , (3.8) where VS , VP , IS , IP are the voltages and currents on the primary and secondary windings. With (3.7) in mind, M can be calculated using the voltages from (3.4) by M = V2 − V4 2pif · 1A . (3.9) Then the coupling coefficient, k, can be calculated using (3.1). In this analysis the current at the ground ring connection (port 6) is explicitly forced to zero by (3.4). To better match how the transformer would be used in a real circuit the voltage at that port should be forced to zero. However, because we are neglecting capacitance and substrate loss, this has little effect on the values obtained for the simplified model. The extracted circuit parameters for the transformer illustrated in Figure 3.5 are listed in Table 3.1. All of the circuit parameters vary only slightly from 1 MHz up to 5.8 GHz, indicating that the simplified transformer model is useful even up to relatively high frequencies for this layout. At 8 GHz and 12 GHz capacitive effects begin to become significant and the inductance and resistance of the primary and secondary windings increase appreciably, which indicates that the self-resonance point is not far beyond 12 GHz. 26 Chapter 3. Bulk-Driven Mixer with Integrated Transformer Balun Table 3.1: Transformer Equivalent Circuit Parameters Frequency LP (nH) RP (Ω) LS (nH) RS (Ω) M (nH) k n 1 MHz 0.446 1.78 1.48 7.42 0.573 0.705 1.82 100 MHz 0.446 1.78 1.48 7.42 0.573 0.705 1.82 1 GHz 0.442 1.83 1.48 7.56 0.573 0.709 1.83 5.8 GHz 0.437 2.29 1.49 9.36 0.580 0.719 1.85 8 GHz 0.445 2.49 1.54 10.5 0.601 0.727 1.86 12 GHz 0.475 3.00 1.70 13.8 0.673 0.748 1.89 3.3.3 Patterned Ground Shield Some of the loss associated with inductors and transformers arises from substrate currents which are induced by the electric fields from the windings which penetrate into the substrate. These electric fields can be blocked from the substrate with the addition of a patterned ground shield below the inductor. Patterning the ground shield prevents the formation of magnetically induced eddy currents within the shield [29]. A side effect of adding a ground is increased shunt capacitance (and thus a lowering of the self-resonant frequency). Patterned ground shields can be effective at blocking the electric field, but they do not prevent the magnetic field from penetrating into the bulk and inducing eddy currents. However, in typical CMOS substrates the conductivity of the bulk is low enough that magnetically induced eddy currents make up only a small fraction of the total loss [8]. The transformer fabricated in this work does not have a patterned ground shield. To determine if this is a source of significant loss, the transformer was simulated in ADS Momentum with a patterned ground on the lowest metal layer. The equivalent lumped element values for the transformer were extracted and are summarized in Table 3.2. As can be seen in the table, there is no significant difference between the two situations. Therefore, at 5.8GHz, a patterned ground shield has negligible effect for this transformer. Table 3.2: Effect of Patterned Ground Shield at 5.8GHz LP (nH) RP (Ω) LS (nH) RS (Ω) M (nH) k n No Shield 0.437 2.29 1.49 9.36 0.580 0.719 1.85 With Shield 0.437 2.29 1.49 9.36 0.581 0.719 1.85 27 Chapter 3. Bulk-Driven Mixer with Integrated Transformer Balun 3.4 Input Match The inductances in the monolithic transformer balun are quite small in comparison to a typical wire-wound transformer, leading to a very small shunt impedance. To increase this reactance, a capacitor can be placed in parallel with either the input or the output of the transformer. The capacitor forms a resonant tank with the transformer, and if the transformer is lossless it would remove the shunt impedance entirely. Unfortunately, both the primary and secondary windings of the monolithic transformer have significant resistance, resulting in a non-negligible shunt impedance even with a resonating capacitor. This is illustrated in Figure 3.8. Req R LC Figure 3.8: Effect of Series Resistance The resulting shunt resistance, Req, is expressed by Req = L2ω2 +R2 R , (3.10) if the value of C is chosen to provide a purely real impedance at ω. This is the resistance that would appear at the input to the transformer if a resonating capacitor were placed at the primary side. If a capacitor is placed at the secondary side, the circuit topology changes slightly and yields a much more complicated expression for Req (assuming a well-coupled transformer, and similar component values to those used in this work). In either case, as long as the winding resistance is low, the shunt resistance is approximately proportional to L2. So placing all (or most) of the resonating capacitance at the secondary can provide a higher shunt impedance. To see this, we first approximate (3.10) with Req ≈ L2ω2 R . (3.11) 28 Chapter 3. Bulk-Driven Mixer with Integrated Transformer Balun Then we express the secondary winding inductance as LS = n 2LP , (3.12) which is valid for a well-coupled transformer, and plug that into (3.11), which results in Req ≈ n4L2P RS , (3.13) where RS is the resistance of the secondary winding. Reflecting this resistance back to the primary results in Rin ≈ n2L2P RS . (3.14) As long as the ratio of the resistance of the secondary winding to the primary winding is less than n2, there is a net improvement. Indeed, in this work, a significant increase in shunt impedance is seen by moving most of the capacitance to the secondary winding. RFin Vbias Vin+ Vin−Cseries Figure 3.9: Matching Circuit Even with this much attention paid to the shunt impedance of the transformer, the high resistance of the monolithic transformer used in this work makes it difficult to achieve high shunt impedances which would be desirable if the primary side of the transformer is to be used as the load inductance of an on-chip low-noise amplifier. However, the winding resistance can be effectively used to achieve a 50 Ω input match. The circuit shown in Figure 3.9 accomplishes this. The vast majority of the capacitance required to resonate out the winding inductance is at the secondary in the form of MIM (metal-insulator-metal) capacitors and either gate capacitance or deep n-well (DNW) capacitance (depending on the mixer). A small amount of capacitance exists at the primary in the form of pad capacitance and a varactor. The varactor provides some fine-tuning to adjust the resonant frequency in case the fabricated device does 29 Chapter 3. Bulk-Driven Mixer with Integrated Transformer Balun not exactly match simulation. The DC block capacitor, Cseries, is also implemented with MIM capacitors and is chosen to be large enough to have negligible resistance in the 50 Ω circuit. The DC block capacitors take up significant area (visible in Figure 5.1) and could be implemented using NMOS capacitors to significantly reduce space. MIM capacitors were chosen for this experiment for simplicity and partly out of concern about the accuracy of the RF models for the NMOS capacitors. 3.5 Simulation The complete mixers are taped out in TSMC’s 0.18 µm CMOS technology for fabrication (see Figure 5.1 for a die micrograph). The layout parasitics are extracted using Calibre and a parameter deck provided by the foundry. The fully extracted layout is simulated in Cadence Spectre. The only portion of the layout that was not extracted using Calibre is the transformer. As mentioned previously, the transformer is modelled in ADS Momentum and the resulting s- parameters are used in the Spectre simulation. The parasitic extraction provided by the foundry does not accurately model inductors and does not extract transformer characteristics. In Cadence Spectre, the periodic steady state (PSS) and quasi-periodic steady state (QPSS) analyses were used. The simulations were done primarily with an IF frequency of 100 MHz to keep the simulation run time and memory usage down to a reasonable level (when using PSS). Occasionally during the design process PSS had to be used for non-linearity analyses (such as compression point or IIP3) instead of QPSS because of conversion issues. PSS works by first performing a transient analysis over one period of the beat frequency which comes as a result of all of the high-level signals applied to the circuit. When doing a compression point or IIP3 measurement there are multiple strong signals so the resulting beat frequency can be very low. Using 100 MHz as the IF frequency (and keeping the spacing between the intermodulation tones in the case of IIP3 high) keeps the run times from becoming excessive when doing PSS analyses. The QPSS analysis is not affected by this because it only treats the LO signal as a strong signal; it treats moderately high input signals in a different manner which only requires the transient simulation to be performed for one LO cycle. The extracted simulation results are presented along with the measured results in Sec- 30 Chapter 3. Bulk-Driven Mixer with Integrated Transformer Balun tion 5.3. The simulated input match for the two mixers is shown in Figures 5.7 and 5.8. Power consumption, conversion gain, P1dB, IIP3, noise figure, and isolation are listed in Table 5.1. 3.5.1 Corner Analysis To maintain mixing operation at corners a common-mode feedback circuit is required (otherwise the gate bias voltage would need to be manually adjusted at the corners to ensure proper mixer operation). A simple common-mode feedback circuit which seeks to set the output common- mode level to 500 mV is added to allow this simulation. The feedback circuit has a gain of 100 for both mixers. No variation is applied to the 500 mV set point for the following corners analysis. With this, the two mixers are simulated at the slow and fast process corners. At the slow corner the temperature is increased to 125 ◦C and the supply voltage is lowered by 10 % to 0.9 V. At the fast corner, the temperature is reduced to −40 ◦C and the supply voltage is increased by 10 % to 1.1 V. These corners represent reasonably well the absolute extremes under which the circuit would likely be operated. Unfortunately, due to software and time limitations, the corner analysis does not take into account process variation which affects the transformer and extracted wiring parasitics. Typical values are used for both of these. However, comparing the fully extracted simulation results to simulation of the bare circuit with only DNW diodes added shows that the wiring parasitics do not have a large effect on the overall performance. They do, however, shift the frequency of the match down slightly (due to added capacitance). Regardless, the most significant parameters affecting the circuits’ operation appear to be those related directly to the intentional components and the DNW diodes, all of which are included in the corners analysis. The effect of process variation on the transformer is expected to have minimal effect on inductance and coupling, but may have an effect on winding resistance (so S11 may be affected slightly and this is not accounted for here). The simulation results are summarised in Table 3.3. Inspection of the results shows that no serious degradation of performance is seen at either of the corners. The input match is also maintained at better than 10dB return loss across the 5.8GHz ISM band (which ranges from 5.725 GHz to 5.875 GHz), except for the slow corner of the RF→Bulk case which just slightly 31 Chapter 3. Bulk-Driven Mixer with Integrated Transformer Balun Table 3.3: Corner Analysis (TT - Typical Corner, FF - Fast Corner, SS - Slow Corner) RF→Gate RF→Bulk TT FF SS TT FF SS I (mA) 0.979 1.27 0.743 0.996 1.286 0.757 CG (dB) 14.6 16.9 11.1 3.25 4.20 1.13 SSB NF @ 10MHz (dB) 19.5 17.3 23.5 28.4 27 31.3 IIP3 (dBm) -4.5 -5.8 -2.3 6.8 6.2 8.9 -10dB S11 low (GHz) 5.470 5.711 5.299 5.389 5.621 5.215 -10dB S11 high (GHz) 6.142 6.389 5.929 6.114 6.387 5.867 misses it. The relatively low quality factor of the transformer leads to a wide bandwidth and aids in maintaining a good S11 across variation. If the S11 performance is not adequate for a particular purpose, the varactor diode which is placed at the input of the transformer can be used to tune the match. Process variation has the most significant effect on the frequency of the match (compared to temperature and supply voltage). So a design could include a DAC to bias the varactor to a pre-programmed value which is determined during manufacturing (either of the RF chip itself, or of a larger product which includes it). 32 Chapter 4 Time-Varying Power Series Analysis The aim of this chapter is to present an analysis of the operation of a bulk-driven mixer core using time-varying power series. Although it takes significant time to apply the analysis to the circuit (to develop the equations and write the code), the resulting simulations run very fast because of their simplicity. It also lends some insight into the operation of the bulk-driven mixers which does not readily appear when performing simulations using tools such as Spectre. A time varying power series is an extension to a simple power series which allows not only the input signal but also the coefficients of the series to vary with time. This lends itself well to the analysis of a mixer because it can be considered to be a single input (the RF signal) and single output (the IF signal) system, but with a time-varying transfer characteristic governed by the current state of the LO signal. The application of a power series neglects memory effects. That is, the output is assumed to depend only on the current state of the inputs, not their history (so inductive and capacitive components cannot be modelled). If memory effects are to be taken into consideration along with the nonlinear effects, a more sophisticated analysis like Volterra series [39] must be used. For the case of a bulk-driven mixer, we shall see that despite this shortcoming, the time-varying power series approach provides useful insight and even some quantitative results. 4.1 Power Series Expressions In this section the general time-varying power series expressions appropriate for the analysis of the bulk-driven mixers described in this work are developed. As stated previously, this method is not capable of taking into account reactive effects, so only the four-transistor mixer core is modelled and the effects of the transformer and parasitic components are not taken into account. 33 Chapter 4. Time-Varying Power Series Analysis 4.1.1 Mixer Half-Circuit To start off on a firm footing, we must precisely define the system which we are modelling. A mixer is a two-input single-output non-linear system, as illustrated in Figure 4.1. Although it is not necessary to treat the two inputs in any special manner, it is best to use the intuitive view that the input signal, Vi(t), is transfered to the output, Vo(t), by a time-varying transfer function, F , whose properties are controlled by the local oscillator, VLO(t). Vo(t) VLO(t) Vi(t) F Figure 4.1: Non-linear Input-Output Representation of a Mixer The input signal, Vi(t) is composed of a time varying portion, vi(t) and a DC portion, VI (and similarly so is the output signal). If the system is memoryless, the output, Vo(t), can be expressed in terms of the two inputs as Vo(t) = vo(t) + VO = F (vi(t) + VI , VLO(t)) , (4.1) where F is some function which describes the input-output characteristics of the system. Due to the symmetrical nature of the mixers in this work, only half of the circuit needs to be simulated. The shaded portion of the complete mixer core shown in Figure 4.2 is analyzed in what follows. It is this half-circuit which the function F describes. The drain currents of M1 and M2 (ID1 and ID2, respectively) add to produce the output signal, Vo(t), so we can define F in terms of them as F (vi(t) + VI , VLO(t)) = −RD [ID1(vi(t) + VI , VLO(t)) + ID2(vi(t) + VI , VLO(t))] . (4.2) It should be noted that because the LO and RF signals are swapped for the two mixers in this work, F is a different function for each mixer. The full small-signal output of the mixer can be obtained simply by removing the even-order 34 Chapter 4. Time-Varying Power Series Analysis IFout LOin or RFin + − −+ RFin or LOin −+ VLO(t) or Vi(t) Vo(t) −+ Vi(t) or VLO(t) −+ M2M1 RD Figure 4.2: Mixer Half-Circuit terms and then doubling vo(t) (to take into account the other half of the differential circuit). The even-order terms are cancelled by the symmetrical nature of the core. 4.1.2 Power Series Expansion Now that we have a clear picture of how the input and output signals are related to each other through the transfer function, F , and the local oscillator input, we can proceed to develop a time-varying power series representation of this relationship. We are primarily interested in the small-signal components of the input and output signals, and not the DC components (although of some practical importance, the DC components are not the focus of this analysis). Following [39], a Taylor series expansion of vo(t) in terms of vi(t) provides us with our time-varying power series. It is vo(t) = vi(t) ∂F ∂vi + v2i (t) 1 2 ∂2F ∂v2i + v3i (t) 1 6 ∂3F ∂v3i + · · ·+ vni (t) 1 n! ∂nF ∂vni + · · · , (4.3) where ∂nF/∂vni , in general, varies with time. The LO signal, VLO(t), does not explicitly appear in this expression, but is contained within the time-varying partial derivatives of F . To make this time dependence clearer, the series can be re-written as vo(t) = vi(t)x1(t) + v 2 i (t)x2(t) + v 3 i (t)x3(t) + · · ·+ v n i (t)xn(t) + · · · , (4.4) 35 Chapter 4. Time-Varying Power Series Analysis where xn(t) = 1 n! ∂nF ∂vni . (4.5) The xn(t) terms can be thought of as time-varying versions of the constant coefficients found in a simple power series. Each of these Xn(t) terms themselves can also be represented as a power series, xn(t) = an,0 + an,1VLO(t) + an,2(VLO(t)) 2 + an,3(VLO(t)) 3 + · · · (4.6) − [ an,0 + an,1(−VLO(t)) + an,2(−VLO(t)) 2 + an,3(−VLO(t)) 3 + · · · ] = 2an,1VLO(t) + 2an,3(VLO(t)) 3 + · · · , where an,m are constants. In (4.6), the second infinite series (in square brackets) is the contri- bution of the second transistor, M2, (which is driven by a reverse polarity version of both the LO signal and the RF signal) to the mixer-half circuit shown in Figure 4.2. This expansion demonstrates that all even-order terms of VLO(t) cancel out, leaving only the odd-order terms. Therefore, if VLO(t) is an odd function of time then so are all of the xn(t) functions. To simplify the calculates, vLO(t) will be chosen to be an odd function of time. The power series represen- tation of the xn(t) terms in (4.6) only serves to provide this conclusion about their character, and will not be explicitly used below. 4.1.3 Output Spectrum The power series obtained above describes the spectrum of the output signal of the mixer. Usually we are only interested in a portion of this spectrum (only one of the mixing products). In this section some further work is performed on the series to arrive at a simpler expression which describes only the portion of the output spectrum that is of interest. To start, we will assume that the LO signal is periodic, which is indeed the case for any frequency conversion application of a mixer. If VLO(t) is and odd function of time (such as VLO(t) = A sin(ωLOt)), and if the xn(t) functions are written as Fourier series (instead of the 36 Chapter 4. Time-Varying Power Series Analysis power series in (4.6)), then vo(t) = vi(t) ∞∑ n=1 x1,n sin(nωLOt) + v2i (t) ∞∑ n=1 x2,n sin(nωLOt) + v3i (t) ∞∑ n=1 x3,n sin(nωLOt) + · · · , (4.7) which can be written in a more compact form as vo(t) = ∞∑ n=1 [ vi(t)x1,n + v 2 i (t)x2,n + v 3 i (t)x3,n + · · · ] sin(nωLOt), (4.8) where the xi,n terms are Fourier series coefficients, determined by xi,n = 2 T ∫ T 0 xi(t) sin(nωLOt), (4.9) and T is the LO period. As discussed above, because VLO(t) is an odd function of time, so are the xn(t) terms, and the cos(nωLOt) terms can be dropped from (4.8). So far the expressions for vo(t), including (4.8), all completely describe the output signal. Usually the IF frequency of interest is at one multiple of the LO frequency away from the RF frequency, so truncating the Fourier series [39] to the first term provides us with our desired IF signal (plus a high-frequency term). As we are interested in only one of the two resulting frequency bands, we can further simplify this to vo(t) = b1vi(t) + b2v 2 i (t) + b3v 3 i (t) + · · · , (4.10) where this equation is considered loose in the sense that the spectrum of vo(t) is understood to be shifted by one LO multiple as compared with vi(t), as in [39]. The coefficients bi are half the value of the coefficients given by xi,1 in (4.9) because of this translation and the fact that we are only looking at half of the total output spectrum. These coefficients are expressed by bi = xi,1 2 = 1 T ∫ T 0 xi(t) sin(ωLOt). (4.11) 37 Chapter 4. Time-Varying Power Series Analysis Equation (4.10) provides a very simple power-series representation of the mixer, where the time-varying aspect of the complete series has been simplified out by focusing our interest on only one of the output products (and further simplified by the use of the loose expression). Although it is not truly an equation, the coefficients, bi, describe the magnitudes of the compo- nents of the output spectra for their respective order of non-linearity. The rest of this analysis focuses on finding xi(t) and the values of bi up to the third order for the two bulk-driven mixer topologies described previously (excluding the transformer balun). 4.1.4 Performance Metrics One of our goals in performing this exercise is to produce some quantitative results which describe the performance of the mixers. To that end, expressions for the supply current, con- version gain, and linearity of the mixers are derived below from the power series expressions that are given above. The expressions below describe the performance of the complete mixer (not just the half circuit), but without the transformer balun. RMS Current The power series developed above focuses on the small signal component of the output and not the supply current (which is a DC term). The current through the load resistor, IRD , is best obtained by applying the LO signal and bias voltage directly to the transistor model and calculating the current, rather than building this into the series. The current through RD in Figure 4.2 is a simple sum of the drain currents of M1 and M2. The total RMS supply current of the mixer is given by IRMS = 2 √ 1 T ∫ T 0 I2RDdt, (4.12) where the factor of 2 accounts for the second half of the mixer. Conversion Gain The linear term in (4.10) represents the conversion gain of the mixer. For very small input signals, the square and cubic terms are vanishingly small, so the output signal is simply the 38 Chapter 4. Time-Varying Power Series Analysis input signal multiplied by b1 (and, of course, translated in frequency). So the conversion gain can be expressed as CG = 20 log(|2b1|), (4.13) where the factor of 2 accounts for the second half of the mixer. This conversion gain is a voltage gain and not a power gain. The input signal does not deliver any power to the mixer because the input impedance is assumed infinite, so a power gain cannot be defined. IIP3 Inspection of (2.6) and (4.10) shows that the magnitude of the third-order product is A3rd-order = 4 3 b3A 3, (4.14) assuming that the two input tones have equal amplitude A. Note that the b3 coefficient is equivalent to the k3 coefficient in (2.6). Equivalently the first order term is A1st-order = b1A. (4.15) To find the intercept point we take the ratio of their magnitudes and set it equal to one, ∣∣3 4 b3A 3 ∣∣ |b1A| = 1, (4.16) and then solve for A2: A2 = 4 3 ∣∣∣∣b1b3 ∣∣∣∣ (4.17) Equation (4.17) can be converted into dBm with the expression IIP3 = 10 log ( 1 2 1 50 1 10−3 4 3 ∣∣∣∣b1b3 ∣∣∣∣ ) − 6, (4.18) where the −6 appears due to the high-impedance termination of the 50 Ω source. Unlike the conversion gain above, the third-order intercept point calculation involves an 39 Chapter 4. Time-Varying Power Series Analysis input power level. The input power level is not the actual input power to the mixer (which is zero), but rather the power level that would be indicated on a 50 Ω signal generator connected to an ideal balun which is providing the RF input for the mixers. It is done this way for ease of comparison with Cadence Spectre simulation output. This also makes comparison to laboratory measurements simpler. The linearity analysis performed here does not take into account nonlinearities beyond the third order. So the discussion in Section 2.2.2 applies and the input-referred 1-dB compression point obtained by the analysis is 9.6 dB below the IIP3 level calculated above. 4.1.5 Transistor Model A key component in modelling a mixer in this manner is the use of an appropriate transistor model. There are several options to choose from in this respect, including the BSIM models [7], a model similar to that used in [39] (which this analysis otherwise follows closely), standard long-channel MOSFET equations [33], or a purely numerical model. The model provided by [39] cannot be used without modification because it does not model the body-effect. The long- channel equations could be used, and would likely provide some insight, but they are known not to match well with the measured data in sub-micron technologies, and so direct comparison to measured or simulated results using realistic models would be dubious at best. In this work, a simple numerical model is adopted and is obtained directly from DC sweeps using Cadence Spectre and the models provided by the foundry. Although Spectre can be used to accurately obtain the linearity performance of the mixer, the real goal here is to find some insight about the non-linearities in the mixer and to verify the validity of this time varying power series method. Extraction of DC parameters DC sweeps are performed on the circuit shown in Figure 4.3 to find the drain current as a function of both VBS and VGS . The sweeps are performed for a fixed supply voltage of VDD = 1 V, which matches the target supply voltage of the mixer prototypes. The resistor in the drain path, RD = 1 kΩ, incorporates the dependence of drain current on drain voltage into our model, to a small degree. The true effect of this dependence on the mixer circuit is 40 Chapter 4. Time-Varying Power Series Analysis slightly different from this model because the drain voltage of a particular MOSFET is not only a function of its own VGS and VBS , but also a function of those parameters for the other MOSFET to which its drain is connected. However, in this structure when a large LO signal is applied, one of the two MOSFETs is mostly off when the other one is on, so the inaccuracy incurred is low. ID VG VB RD VDD Figure 4.3: DC Model Extraction The DC sweeps performed on the circuit in Figure 4.3 span −0.5 V ≤ VGS ≤ 1.8 V and −1.0 V ≤ VBS ≤ 1.0 V, and the sweep step size is chosen to produce a 200 by 200 element result matrix. Such a large VBS range is included to ensure that simulations can be performed with large RF or LO signals applied to the bulk. The model from which the curves are extracted from includes the drain-bulk and source-bulk diodes. The parasitic deep n-well diode that would exist in an actual implementation (to allow access to the bulk of individual transistors), is not modelled. The only significant effect that this diode has on the circuit is added capacitance on the bulk connection, and capacitance is not modelled here. 4.2 Numerical Analysis To apply the analysis described in Section 4.1 above to the mixers in this work, numerical values for the xn(t) functions must be found. These functions are derivatives of input-output relationship F with respect to the input signal. Inspecting Equations 4.2 and 4.3 indicates derivatives of the MOSFET drain current with respect to either VGS (for the RF→Gate case) 41 Chapter 4. Time-Varying Power Series Analysis or VBS (for the RF→Bulk case) must be used. This is accomplished with the use of central differences, as described below. 4.2.1 Central Differences The derivative of a function can be found numerically using one of many possible formulations of finite differences [2, pp. 877-884] [3, pp. 19-23]. In this work, central differences are used rather than forward or backward differences because the result is slightly more accurate. In general, the n-th order derivative of a function can be expressed in terms of the central difference δnh [f ](x) as dnf dxn = δnh [f ](x) hn +O(h2) ≈ δnh [f ](x) hn , (4.19) where O(h2) is an error term, and the central difference is given by δnh [f ](x) = n∑ i=0 (−1)i ( n i ) f ( x+ (n 2 − i ) h ) . (4.20) In these expressions, h is the spacing between sample data points. For odd values of n the resulting expressions for the derivatives evaluate f at non-integer multiples of h, which is problematic if the function is discrete. To remedy this, the central difference expressions evaluated at ±h/2 are averaged, providing an expression with only integer multiples of h. The resulting central difference expressions for the first three derivatives are df dx ≈ f(x+ h)− f(x− h) 2h , (4.21) d2f dx2 ≈ f(x+ h)− 2f(x) + f(x− h) h2 , and (4.22) d3f dx3 ≈ f(x+ 2h)− 2f(x+ h) + 2f(x− h)− f(x− 2h) 2h3 . (4.23) These central difference expressions are implemented in GNU Octave 4 and applied to the DC sweep data from Section 4.1.5, as discussed in the following sections. 4GNU Octave is an open-source mostly MATLAB R© compatible numerical computation program. It is avail- able at: http://www.gnu.org/software/octave/ 42 Chapter 4. Time-Varying Power Series Analysis 4.2.2 RF→Gate Analysis For the RF→Gate case the RF signal is applied to the gates, so the derivatives of F in the power series expression must be taken with respect to VGS . For this case, the xn(t) functions in (4.5) are then xn(t) = 1 n! ∂nF ∂vni = 1 2n 1 n! ( ∂nID1 ∂vnGS1 ∣∣∣∣ VBS1= VLO(t) 2 ,VGS1=Vbias − ∂nID2 ∂vnGS2 ∣∣∣∣ VBS2=− VLO(t) 2 ,VGS2=Vbias ) , (4.24) where Vbias is the DC bias level of the gate (the LO signal). The 1/2 n term arises due to the differential nature of the RF input. The periodic bias imposed by the LO drive is included by taking the derivatives at this time-varying bias point on the ID characteristic, and is explicitly indicated in (4.24). The GNU Octave code implemented for this work achieves this by finding the first three central difference derivatives of ID at all of the data points in the numerical transistor model with respect to VGS . These results are then interpolated to find the derivative at the specified gate bias (Vbias) and for each value of VLO(t) (for one LO period). Once the xn(t) are found, the bi coefficients are computed by numerically integrating (4.11). The initial computation of derivatives at all points is excessive if the performance of the circuit is to be evaluated at one bias point and one LO drive level only. However, if multiple bias points and/or drive levels are of interest, then performing all of the derivatives once allows the simulation to be performed at each new operating point very quickly. All that is required at each operating point is an interpolation of the previously calculated derivatives, rather than recalculating the derivatives. RF→Gate Analysis Results The xn(t) curves for the RF→Gate case for a LO power level of 2 dBm and gate biasing of 0.52 V (such that the circuit consumes approximately 1 mW) are shown in Figure 4.4. The curves are plotted for one LO period. The bn coefficients in (4.10) are a measure of how well correlated the associated xn(t) curve is to the LO signal (see (4.11)). So, intuitively, the shape of the x1(t) curve in the figure shows good correlation with the LO signal fundamental and 43 Chapter 4. Time-Varying Power Series Analysis therefore |b1| is large and there is good gain for this selection of bias and LO level (note that the curves are scaled arbitrarily, so only qualitative discussion can follow from them). With this in mind, an inspection of these curves under various bias conditions provides intuition about how changing the bias changes the gain and linearity performance of the mixer. 0 20 40 60 80 100 120 140 160 180 x1(t) x2(t) x3(t) Time (ps) A rb it ra ri ly S ca le d U n it s Figure 4.4: RF→Gate xi(t) The performance of the mixer over a range of gate bias voltages and LO drive levels is shown in Figure 4.5. A few general conclusions can be drawn from the figures. Perhaps not surprisingly, the current draw increases with increased gate bias and to a much lesser extent by the LO drive level, but at very high gate bias voltages the LO level has virtually no effect on bias current. At high gate bias levels the transistors spend most of their time in deep triode, substantially reducing the gain of the mixer and also reducing the effect of the LO drive (applied to the bulk). The IIP3 plot shows a spike at two different gate bias levels. The peaks in the plot appear quite ragged due to the granularity of the gate and LO drive sweeps. One peak occurs at very low gain, and upon closer inspection also shows dips. The existence of both the peaks and dips at low gain is likely a result of the calculation accuracy and the ratio b1/b3 becoming poorly defined in (4.18). The peak at the lower gate bias voltage can be explained by the zero crossing of ∂Id/∂VGS . The dip in the gain plot (Figure 4.5a) near 0.58 V is particularly interesting. This null exhibits itself in the x1(t) curve as a progressively deeper dip, such as the dip that is apparent 44 Chapter 4. Time-Varying Power Series Analysis 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 -4 -2 0 2 4 -10 -8 -6 -4 -2 0 2 4 6 8 10 VRF−bias (V) Plo (dBm) CG (dB) (a) 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 -4 -2 0 2 4 -20 -10 0 10 20 30 40 VRF−bias (V) Plo (dBm) IIP3 dBm (b) 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 -4 -2 0 2 4 0 0.5 1 1.5 2 2.5 VRF−bias (V) Plo (dBm) I (mA) (c) Figure 4.5: RF→Gate Bias Voltage and LO Power Sweeps: (a) Conversion Gain; (b) IIP3; (c) Supply Current. in the x1(t) case for the RF→Bulk case (Figure 4.7). As the gate bias is increased beyond the gain null, the dip in x1(t) becomes very large (it takes on the appearance of x2(t) in Figure 4.4). As previously discussed, the gain is proportional to the b1 coefficient, and the b1 coefficient is a measure of the correlation between x1(t) and the LO signal. So as the dip in x1(t) increases, there is a point where x1(t) shows exactly zero correlation with the LO drive signal and the gain drops to zero. For higher gate biases, the deep dip in x1(t) shows up as a sign change in b1 (the correlation goes negative), and the phase of the output signal is inverted relative to the lower bias case. The physical explanation for this is that as the gate bias voltage is raised the transistors 45 Chapter 4. Time-Varying Power Series Analysis spend less time in the off state and for large enough bias voltages never turn off (and spend more time in the triode region). So at high bias levels, the LO voltage which would normally bring the transistors out of cut-off now puts them further into triode. Also, the LO voltage which previously turned off the transistors brings them further out of triode and actually increases their gain. Overall then, at high gate biases, the affect of the LO signal on the gain is exactly inverted compared to the lower bias case. RF→Gate Results Compared to Spectre Output To see how well this analysis matches a trusted circuit simulator, and to determine to what frequency the power series analysis results are valid, the same circuit was simulated in Spectre. The results of this simulation are plotted in Figure 4.6 under the same gate bias and LO drive conditions (0.52 V and 2dBm, respectively). -8 -6 -4 -2 0 2 4 6 8 10 100000 1e+06 1e+07 1e+08 1e+09 1e+10 0.92 0.94 0.96 0.98 1 1.02 1.04 1.06 1.08 1.1 1.12 1.14 CG IIP3 Current Frequency (Hz) d B or d B m m A Figure 4.6: RF→Gate Conversion Gain, IIP3, and supply current vs fLO (Spectre Output) At this operating point, the power series analysis predicts a conversion gain of 8.8 dB, an IIP3 of -6.6 dBm, and a current draw of 1.2 mA. These values match extremely well with those in Figure 4.6 for low frequencies. At frequencies above 1 GHz the results start to deviate strongly from the power series calculation. This can be attributed to parasitics. 46 Chapter 4. Time-Varying Power Series Analysis 4.2.3 RF→Bulk Analysis For the RF→Bulk case the RF signal is applied to the bulk, so the derivatives of F in the power series expression must be taken with respect to VBS . For this case, the xn(t) functions in (4.5) are then xn(t) = 1 n! ∂nF ∂vni = 1 2n 1 n! ( ∂nID1 ∂vnBS1 ∣∣∣∣ VGS1=Vbias+ VLO(t) 2 ,VBS1=0 − ∂nID2 ∂vnBS2 ∣∣∣∣ VGS1=Vbias− VLO(t) 2 ,VBS2=0 ) , (4.25) where Vbias is the DC bias level of the gate (the LO signal). Similar to the RF→Gate case, to implement this equation, we first find the central difference derivatives of ID with respect to VBS at all data points in the numerical transistor model. These results are then interpolated at the time varying bias point to produce the xn(t) functions. RF→Bulk Analysis Results The xn(t) curves for the RF→Bulk case for a LO power level of 2 dBm and gate biasing (0.25 V) such that the circuit consumes approximately 1 mW are shown in Figure 4.7. Performance characteristics for a range of bias voltages and LO drive levels are shown in Figure 4.8. 0 20 40 60 80 100 120 140 160 180 x1(t) x2(t) x3(t) Time (ps) A rb it ra ry U n it s Figure 4.7: RF→Bulk xi(t) In this case, the x1(t) curve exhibits a dip, suggesting that it may be possible to adjust a parameter to improve the gain slightly. Inspection of Figure 4.8a verifies that at the specified bias and LO drive level the gain is not quite optimal (the operating point is slightly away 47 Chapter 4. Time-Varying Power Series Analysis 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.28 0.30 -4 -2 0 2 4 -10 -9 -8 -7 -6 -5 -4 -3 -2 VLO−bias (V) Plo (dBm) CG (dB) (a) 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.28 0.30 -4 -2 0 2 4 -5 -4 -3 -2 -1 0 1 2 VLO−bias (V) Plo (dBm) IIP3 dBm (b) 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.28 0.30 -4 -2 0 2 4 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 VLO−bias (V) Plo (dBm) I (mA) (c) Figure 4.8: RF→Bulk Bias Voltage and LO Power Sweeps: (a) Conversion Gain; (b) IIP3; (c) Current. from the peak of the plot). However, inspection of Figure 4.8b shows that this operating point provides slightly better linearity. It is unclear why the x3(t) curve (which is responsible for IIP3) is not smooth near the 1/4 cycle and 3/4 cycle locations on the plot. It most likely stems from an anomaly which has been observed in the TSMC BSIM model (illustrated in Figure 4.9). The data for this figure was extracted using a DC sweep in Spectre. The figure shows a smooth looking ID versus VBS curve and a fairly smooth ∂ID/∂VBS curve (slight bumps are seen near VBS = 0 V and VBS = 0.25 V). Those bumps cause very large abrupt changes in the ∂ 2ID/∂V 2 BS and ∂3ID/∂V 3 BS curves. Furthermore, for the RF→Bulk case, the simulation is performed with a 48 Chapter 4. Time-Varying Power Series Analysis VBS bias of 0 V, which lands right on top of a steep area of those anomalies. Based on this observation, accurate predictions on the non-linear performance of the RF→Bulk case cannot be extracted from this transistor model. Regardless, it is worth taking a look at the swept plots -1 -0.5 0 0.5 1 ID ∂ID/∂VBS ∂2ID/∂V 2 BS ∂3ID/∂V 3 BS VBS A rb it ra ry U n it s Figure 4.9: BSIM Model Anomaly of Figure 4.8. The supply current dependency (Figure 4.8c) on gate bias and LO drive level is quite different than the RF→Gate case. Here, the supply current is a strong function of LO power and to a much lesser degree the gate bias voltage. An explanation for this lies in the fact that all of these gate bias voltage levels are below the transistor’s threshold voltage, so the power consumption comes from the LO drive bringing the transistor out of cut-off. The conversion gain (Figure 4.8a) does not show an inversion as in the RF→Gate case. Related to the explanation of the current draw characteristic, this is due to the gate bias being kept low enough to prevent significant time spent in the triode region. However, the decrease in gain as the LO bias is increased beyond peak is likely explained by larger excursions into the triode region with larger LO drive level. The IIP3 performance (Figure 4.8b) shows very little variation with bias and LO drive level. Based on the discussion of the anomaly above, it is best not to draw conclusions from this. However, if this plot does describe actual behaviour, then it may be due the fact that over the range of LO drive levels and gate bias the mixer is operating in a similar regime (as opposed to the case of the gain inversion seen in the RF→Gate case). 49 Chapter 4. Time-Varying Power Series Analysis RF→Bulk Results Compared to Spectre Output As done with the RF→Gate case, the results are compared with a Spectre simulation of the same circuit. The results of that simulation are shown in Figure 4.10. -10 -5 0 5 10 15 20 100000 1e+06 1e+07 1e+08 1e+09 1e+10 0.72 0.74 0.76 0.78 0.8 0.82 0.84 0.86 0.88 CG IIP3 Current Frequency (Hz) d B or d B m m A Figure 4.10: RF→Bulk CG, IIP3, and current vs fLO (Spectre Output) As expected, the conversion gain that is predicted by the power series method (-3.46 dB) matches quite closely with the Spectre simulation for low frequencies (there is, however, a slight change in bias current from 0.978 mA for the power series method). The predicted IIP3 is −1.54 dBm and is quite different than the Spectre simulation. This is likely attributable to the above mentioned anomaly and a different simulation method. 50 Chapter 5 Performance Measurement The two mixers were fabricated by TSMC in a 0.18µm CMOS process. A micrograph of a fabricated die is shown in Figure 5.1. Visible in the micrograph are additional test structures, including a separate transformer (of the same layout as the ones used in the mixers), an inductor, a short portion of top-metal trace, a varactor, and a transistor for the measurement of S11 looking into the bulk. They were placed to allow exploration of simulation and measurement discrepancies if it became necessary. The measurement and simulation results were close enough that specific use of these test structures was not made. RF Gate RF Bulk IF Out LO In RF InRF In Core Mixer Mixer MIM Matching Caps Figure 5.1: Fabricated Mixer Each mixer occupies approximately 0.15 mm2, including the 50 µm guard space surrounding the balun. The transformer occupies the majority of the space, with the MIM matching caps being the next largest. The larger MIM caps which are near the RF inputs are the DC block capacitors (Cseries in Figure 3.9), and could be made using a much smaller (physically) MOS cap instead to conserve space. The MIM capacitors responsible for matching are visible between 51 Chapter 5. Performance Measurement the transformer and the mixing core, and are clearly much smaller than the DC blocks. They occupy a similar area to the four transistors which make up the mixer core. The measurement setup and results are discussed in the following subsections. 5.1 Measurement Setup The fabricated mixers were tested using on-die probing on a Cascade Microtech RF-1 probe station. A total of four probes was used. Two GGB Industries ground-signal-ground (GSG) probes were used to provide the RF input (one for each mixer to simplify the test setup). The LO drive was provided by a SUSS Microtech GSGSG probe. A Cascade Microtech Eyepass probe with a PGLLLLGP pinout (the L indicates a low-frequency signal and P indicates power) was used to measure the IF output and to provide power and biasing to the mixers. Several pieces of RF test equipment were used to perform the measurements. The LO and RF test signals were provided by Agilent RF signal generators (83752A, 83732B, and an 8593E). The IF output was measured using both a high speed oscilloscope (Agilent DSO81304A) and a spectrum analyzer (Agilent PSA E4440A). Noise measurements were also made using the PSA. S-parameter measurements were made with an Agilent 8510C vector network analyzer. Details of the measurement setup are provided below. 5.1.1 Instrumentation Amplifier The IF output impedance of the fabricated mixers is 1kΩ (for each half of the differential outputs). To allow connection to standard 50Ω RF test equipment, a custom instrumentation amplifier is used to drive the equipment and present mixer the IF outputs with a high impedance (so that the measurement setup does not affect the performance of the mixers). The schematic of the instrumentation amplifier is shown in Figure 5.2. At the output of the amplifier there is a DC blocking capacitor to protect the test equipment from large DC signals which may accidentally appear at the output of the amplifier. The overall gain of the amplifier when connected to a 50Ω load is very close to unity. The amplifier was implemented with high- bandwith National Instruments LM7171 opamps and R = 1kΩ. 52 Chapter 5. Performance Measurement + − + − + − R R RR R R 2R 50Ω 150nF Vout Vin+ Vin− Figure 5.2: Instrumentation Amplifier The amplifier was simulated in ngspice5 and measurements were performed in the lab to determine if the actual gain of the amplifier is unity at the frequencies of interest. Indeed, the amplifier was measured to differ from unity gain by a small fraction of a decibel for frequencies at and below 10MHz (at higher frequencies the amplifier has some loss). Details about de- embedding the noise contribution of the amplifier are discussed below in Section 5.2. 5.1.2 Local Oscillator Generation Both of the fabricated mixers require a balanced LO drive at a frequency of 5.79 GHz (the precise frequency is not critical, but this frequency is chosen to match simulation). To create the balanced LO, the structure illustrated in Figure 5.3 is used. The required 180◦ phase difference is achieved using a trombone (a short piece of transmission line whose length is mechanically adjustable). The output of the setup is measured using an Agilent DSO81304A high-speed oscilloscope and the trombone is adjusted until the 180◦ phase requirement is met (at the input of the GSGSG probes marked as “Calibration Point” in the figure). The signal generator power level is also adjusted until a −1dBm signal level (plus the loss of the wafer probes) is measured at each LO output. At the calibration point are SMA connectors which, after calibration, are connected directly to the wafer probe. Although the RF trombone which was used (Connecting Devices Inc. 5052-2) is only spec- ified for operation up to 2 GHz, it is found that using this structure the signal amplitude balance at the LO frequency of 5.79 GHz is within ±0.5 dB and the phase balance is within 5◦. The phase balance can be achieved with arbitrary precision with careful adjustment as long as 5Ngspice is an open-source circuit simulator based on Berkeley SPICE. It is available at: http://ngspice.sourceforge.net 53 Chapter 5. Performance Measurement Signal Generator Power Splitter 6dB 6dB Trombone (180◦ shift) SUSS MicroTech GSGSG ProbeCalibration Point Bias TBias TVLObias VLObias Figure 5.3: Balanced LO Generation nothing else is moved. Measurements were performed periodically to check the status of the LO drive and the phase balance was kept within 5◦. The RF→Bulk mixer, in particular, needs a DC bias on the LO drive because it is directly connected to the transistor gates. Two RF bias-Ts are included to provide it (VLObias in Figure 5.3). 5.1.3 Dual Signal RF Source To allow measurement of IIP3 two RF signals are required at the input of the mixer. To achieve this, a power combiner is used to combine the output of two RF signal generators. To ensure that the signal from one generator does not feedback into the other generator and interfere with its output power measurement, attenuators are added between the generators and the combiner, as shown in Figure 5.4. These attenuators provide an additional 20dB of isolation 54 Chapter 5. Performance Measurement on top of the isolation provided by the combiner. Signal Generator 1 Combiner 10dB GGB Industries GSG Probe Calibration Point Signal Generator 2 10dB Bias T VRFbias Figure 5.4: RF Source Setup As with the LO generation structure, the RF source is calibrated up to the place marked “Calibration Point”, which is an SMA termination to be connected directly to the RF probe. The probe loss (provided by the manufacturer) is used to determine the actual signal strength reaching the chip. Both mixers optionally require a DC bias at the RF input to adjust the input match (see Figure 3.9). This is provided with a bias-T (VRFbias in Figure 5.4). 5.2 Noise Figure De-embedding The noise figure of the mixers cannot be measured directly because they are situated behind the instrumentation amplifier in the test setup, which is a significant source of noise. Instead, the noise figure of the entire setup (Figure 5.5) must be measured and then the noise figure of the mixer itself must be de-embedded. To achieve this, the instrumentation amplifier must be characterized and then its effect on the system should be accounted for. 55 Chapter 5. Performance Measurement Nm, Gm Ni Na To Meter LO Figure 5.5: Mixer Noise De-Embedding Instrument Noise Source NR 50Ω Ni Na To Meter 50Ω Figure 5.6: Instrumentation Amplifier Noise Test Circuit The noise contribution of the instrumentation amplifier was determined by placing it in a simple test circuit (Figure 5.6) and measuring the resulting noise figure with a noise figure meter. The noise contribution of the amplifier, Na, can then be calculated by solving Fa = Si/Ni So/No = No GaNi = NiGa +NRGa +NaGa GaNi = Ni +NR +Na Ni , (5.1) which provides us with, Na = Ni(Fa − 1)−NR, (5.2) where Fa is the measured noise factor of the test circuit, NR is the noise associated with the load resistor, and Ga is the gain of the amplifier. The input noise, Ni, and the noise from the resistor, NR, are both equal to kBTB (Boltzmann’s constant, kB, temperature, T , and bandwidth, B) due to the matched nature of the circuit. In this analysis the noise contribution of the amplifier is treated as an additive voltage noise source. Any linear two-port circuit can be modelled by a noiseless circuit preceded by a voltage noise source (in series with the input) and a current noise source (in parallel with the input) [32, p. 221]. The input impedance of the instrumentation amplifier is very large, so when a source is connected (with relatively low 56 Chapter 5. Performance Measurement output impedance), the effect of this current source is low. Once the noise contribution of the instrumentation amplifier is known, the noise figure of the mixer itself can be calculated. The noise contribution of the mixer, Nm, can be calculated from the measured noise figure of the system by solving F = Si/Ni So/No = Na +NiGm +NmGm GmNi (5.3) for Nm, Nm = Ni(F − 1)− Na Gm , (5.4) where F is the measured noise figure of the circuit in Figure 5.5. Once Nm is known the noise figure of the mixer itself, Fm, can be calculated as Fm = Si/Ni Som/Nom = SiNom GmSiNi = Ni +Nm Ni , (5.5) where Som/Nom is the signal-to-noise ratio at the output of the mixer and Gm is the gain of the mixer. As is expected, the gain of the instrumentation amplifier (which is the last stage of the circuit) does not play a role in the noise figure calculation. 5.3 Measurement Results The majority of the measurement results are summarized in Table 5.1. The table compares the measured and simulated results of the two mixers in this work, and also provides performance metrics for a few other mixers with similar characteristics. There is no one metric for a mixer which defines its quality, and for some applications different metrics may have precedence over other metrics. As an example, the linearity of a mixer used as part of a multi-channel transmitter may be much more important than its noise figure. As the target application of these mixers is not precisely defined, a figure of merit (FoM) [12] is adopted to provide a fair and unbiased comparison of the various mixers. The FoM is 57 Chapter 5. Performance Measurement Table 5.1: Performance Summary and Comparison RF→ Bulkβ RF→ Gateβ [12]α [24]α [11]α,γ[42]α Technology (µm) 0.18 0.18 0.18 0.09 0.35 0.5 VDD (V) 1 1 0.8 1.2 0.9 1 P (mW) 1 1 0.4 1.8 4.7 0.18 RF (GHz) 5.8 5.8 1.9 2.15δ 0.9 6.9 Gain (dB) 3.4/−0.8 14.7/13.6 1 3.2 2 6 P1dB†(dBm) 0.9/6.5 −13.9/−14 * −13.3 −8 −16 IIP3 (dBm) 11/15.3 −4.3/−5.2 −9 −2.1 3.5 −2 SSB NF (dB) 28/37 20/26 11 20.4 13.5 21‡ LO→RF Isolation (dB) >80/67 >80/50 * * * 29 FoM 212/203 216/208 201 195 194 217 † Input referred. ‡Converted from DSB. * Not specified. αMeasured Results. β Simulated / Measured. γ Not a bulk-driven topology. δ Nominal results quoted at RF=2.15 GHz, but it operates up to 20 GHz. defined as FoM = 20 log(fRF ) +G−NF + IIP3− 10 log(P ), (5.6) where fRF is the RF frequency in Hz, G is the conversion gain in dB, NF is the noise figure in dB, IIP3 is in dBm, and P is the power consumption in Watts. The FoM is a decibel sum of important metrics which describe the mixer performance, with no weighting on any particular value. Most of the measurements are made at an LO frequency of 5.79 GHz and an RF frequency of 5.791 GHz, providing an IF frequency of 1 MHz, with the exception of the input-referred third-order intercept point. IIP3 is measured with two input tones at 5.793 GHz and 5.794 GHz so that the intermodulation tones are well defined. The exact frequencies which are used for the IIP3 measurement should have very little effect on the measurement outcome because of the wide output bandwidth of these mixers. Due to equipment limitation the noise figure is measured at 10MHz (accurate measurements could not be made at lower frequencies). The low IF frequency of 1 MHz is used for most measurements to remove uncertainty in the gain of the IF amplifier at higher frequencies. Simulation shows that the mixers themselves have relatively flat frequency responses well beyond 10MHz, so the measurement results at 1MHz are also valid at 10MHz where the noise figure is measured. 58 Chapter 5. Performance Measurement The results listed in the table and S11 (input match) are discussed in the following subsec- tions. 5.3.1 Gain The measured and simulated gain of the two mixers match reasonably well, as indicated in the table. This is particularly true for the RF→Gate case where they differ by only 1 dB. Considering that simulation of the circuit involves electromagnetic modelling of a monolithic transformer based solely on material physical properties and layer thickness provided by the foundry (and without any prior measurements to verify the accuracy of the transformer model), a 1dB discrepancy on a gain of approximately 14 dB is an excellent result. The measured gain of the RF→Bulk case is substantially lower (a difference of 4.2 dB) than the simulated gain, which indicates that the transistor models provided by the foundry may not accurately predict the small-signal behaviour of the bulk contact. The bulk is not usually used as a signal path (it is either attached directly to ground or to the source of the transistor), so it is reasonable to expect that this connection is not as carefully characterized as the other terminals. This inaccuracy in modelling does not appear to significantly effect the RF→Gate case. A justification for this is that a very large signal (the LO), rather than a small one, is applied to the bulk in this mixer. With such a large signal on the bulk, the bulk transconductance that is predicted by the model is of less concern here, and the affect that the LO signal has on the transistor’s threshold voltage (and therefore the gate transconductance) plays a much more significant role in defining the gain of the mixer. 5.3.2 Input Match The excellent input match achievable with the transformer balun is one of this design’s strong points. The measured input match compared with the simulated input match for both mixers is shown in Figures 5.7 and 5.8. The vertical dotted lines in Figure 5.7 are the bottom and top of the 5.8GHz ISM band (5.725GHz and 5.875GHz respectively). These are also marked on the Smith charts in Figure 5.8. The results clearly indicate both an excellent match and an excellent correlation between simulated and measured results, particularly for log plot of the 59 Chapter 5. Performance Measurement RF→Gate case. Without any varactor tuning (refer to Figure 3.9) both of the mixers provide better than 10dB return loss. The RF→Bulk case is tuned slightly high in frequency (suggesting that the model of the DNW diodes or the bulk itself is not precise). A varactor bias of 0.54 V returns the match to line up well with the simulated results (shown by the “Tuned” line). The conversion gain of the RF→Bulk mixer was measured with and without the varactor bias and any difference in performance was virtually undetectable. -30 -25 -20 -15 -10 -5 0 5 10 0 2 4 6 8 10 12 RF→Bulk (No Tuning) RF→Bulk (Tuned) RF→Bulk (Simulated) RF→Gate (Simulated) RF→Gate (No Tuning) Frequency (GHz) S 11 (d B ) Figure 5.7: S11 Measurements The discrepancy between the measured and simulated S11 for the RF→Bulk case (illustrated best in the log-magnitude plot) falls within reasonable limits based on the corners analysis (Table 3.3). However, if process variation were responsible for the shift in frequency then one would expect that both mixers would be similarly affected. This is not the case, so inaccuracy of bulk modelling is the most likely explanation. The Smith chart representation of the RF→Gate input match (Figure 5.8b) shows that there is some difference in actual impedance values between the measured and simulated results, despite the excellent log-magnitude results. The measured results show a slightly higher input impedance in the desired frequency band. There are a few possible explanations for this, including: • The trace resistance between the RF input pad and the transformer is underestimated in simulation. The parasitic extraction tool does not take into account skin depth, so the frequency dependence of resistance is not taken into account. 60 Chapter 5. Performance Measurement 5.725GHz 5.8GHz 5.875GHz 0 1 -1 0.3 -0.3 0 10.3 3 -20 -10 -5 Measured (No Bias) Simulated Measured (0.54V Bias) (a) RF→Bulk 5.725GHz 5.8GHz 5.875GHz0 1 -1 0.3 -0.3 0 10.3 3 -20 -10 -5 Measured Simulated (b) RF→Gate Figure 5.8: S11 at RF Input • The winding resistance of the transformer is lower than simulated, resulting in a higher shunt impedance at resonance. • The series resistance of the gate and source terminals of the transistors (and/or the MIM capacitors) are lower in reality than in simulation, resulting in a higher quality tuned circuit and again a higher shunt impedance. • A slight difference in simulated and actual coupling between the transformer windings. • A combination of the above. The Smith chart representation of the RF→Bulk case (Figure 5.8b) appears to show better correlation than the RF→Gate case. However, differences that are visible in the RF→Gate case may be masked by the change in resonant frequency of the match in the RF→Bulk case. The curves are closer together, but the frequency points on the measured (without varactor bias) and simulated curves are not. Adjusting the varactor to compensate involves changing the capacitance at the input of the transformer (rather than at the output where the bulk is), which also changes the overall characteristics of the match, so the proximity of the simulated 61 Chapter 5. Performance Measurement and measured (with varactor bias) curves does not indicate quite as close a match as it may seem at first glance. That said, all of these variances in the input match are quite minor. The above discussion is meant to illustrate where the minor inconsistencies may originate from. 5.3.3 Isolation The measured isolation between the LO and RF ports is quite substantial at 50 dB for the RF→Gate case and 67 dB for the RF→Bulk case. This high level of isolation makes these mixers potential candidates for low-IF or zero-IF receivers because of the low DC offset which would be induced by the LO signal feeding back into the RF path. 5.3.4 Linearity Figure 5.9a shows the P1dB measurement results, and Figure 5.9b shows the IIP3 measurement results. Although it is not strictly necessary to take multiple measurements to determine IIP3, doing so helps to verify the accuracy of the measurements. As illustrated in the figure, all three of the measurement points land on the 1 dB/dB and 3 dB/dB extrapolated lines. If they had not landed on the lines it would indicate that there was either excessive noise in the measurement (so the measure power is higher than it should be), or that the spur is not a result of a third-order non-linearity. (a) 1 dB Compression Point (b) Third-order Intercept Point Figure 5.9: Non-linearity Measurements 62 Chapter 5. Performance Measurement The measured gain of the RF→Bulk case is lower than simulation by approximately 4dB, and the measured IIP3 and P1dB are approximately 4dB higher than simulation. This would be consistent with a pure loss of 4dB being added between the RF input and the bulk connection. This is further evidence that it is specifically inaccuracy in bulk modelling which is responsible for the measurement discrepancies. As a final note, it is interesting that for both mixers the measured input-referred 1 dB compression point and input-referred third-order intercept point differ by 8.8 dB. This suggests that a third-order nonlinearity plays a primary role in defining the 1 dB compression point (as discussed in Section 2.2.2). 5.3.5 Noise The noise performance of these mixers compared to other mixers is relatively poor. The RF→Bulk case is likely too poor for most practical applications, however the RF→Gate case noise figure is low enough that it can be used. For example, if preceded with an LNA with a gain of 25 dB and a noise figure of 2 dB, the cascaded noise figure of the LNA/RF→Gate system would be 4.5 dB. Such a value might be low enough to be acceptable for RF applications such as sensor networks or implantable devices. Additionally, these mixers have relatively high linearity considering their gain and power consumption, so preceding them with high gain LNAs is possible. Simulation shows that the flicker noise corner frequency is approximately 10MHz for both mixers. Above 10MHz the noise figure does not improve appreciably from the results shown in the table, and below 10MHz it rises sharply, following the 1/f characteristic. Existing research results [25] show that in switched circuits like mixers, flicker noise is much reduced compared with simulation results. So the discrepancy between measured and simulated noise figures is not likely related to flicker noise. Indeed, a slightly lower noise figure was expected when measured. The noise performance of bulk-driven mixers is something that could be explored in future research. 63 Chapter 5. Performance Measurement 5.3.6 Performance Summary The overall performance of the two mixers, as judged by the FoM in Table 5.1, are fairly close (the measured FoM differs by 5 overall for the two mixers). Also using the FoM, it is seen that the mixers perform well overall compared to other CMOS mixers. However, as mentioned previously, the noise performance of the RF→Bulk case is quite poor compared to the RF→Gate which is a serious hindrance for use in a radio receiver. Based on the FoM and the overall performance parameters, the RF→Gate structure is clearly an improvement over the RF→Bulk structure. Comparing simulated and measured gain in Table 5.1 to the gain of the mixer core (shown in Figure 3.4) shows that the transformer balun significantly increases the conversion gain of the mixer. The transformer also provides an excellent input match, as discussed above. 64 Chapter 6 Conclusion The design, analysis, and performance measurement of two bulk-driven mixers with on-chip transformer baluns has been presented. The mixers are found to match or exceed the perfor- mance of comparable mixers based on a figure-of-merit comparison, which takes into account important performance metrics. The use of a transformer balun has been demonstrated to provide an excellent input impedance match and increase the gain of the mixers. The balun also provides a single-ended to balanced conversion, which may be helpful when connecting to an off-chip image-reject filter. The RF→Gate mixer topology achieves a measured input-referred P1dB of −14 dBm, an IIP3 of −5.2 dBm, a gain of 13.6 dB, a NF of 26 dB, and an LO-to-RF isolation of 50 dB. The measurement results of the RF→Bulk topology are an input-referred P1dB of 6.5 dBm, an IIP3 of 15.3 dBm, a gain of −0.8 dB, a NF of 37 dB and an LO-to-RF isolation of 67 dB. The high noise figures of these mixers can be mitigated to some degree by the addition of a high-gain low-noise amplifier. That their FoM is high despite the high noise figure indicates that their linearity performance is above average, thus supporting an increase in LNA gain. A power series analysis has also been presented which illustrates the operation of the mixer core (on an LO cycle-by-cycle basis), and reveals some of the key non-linear effects which exist in bulk-driven mixers. In addition to the insight afforded by the analysis, it runs very quickly, thereby allowing broad sweeps of operating parameters to be performed. The analysis also reveals an anomaly (indicated in Figure 4.9) with the transistor model provided by the foundry which, due to its nature, has a direct impact on the linearity calculations which are performed as part of the analysis. 65 Chapter 6. Conclusion 6.1 Future Work An area which warrants some future investigation is the noise performance of bulk-driven mix- ers. The noise performance of these mixers is significantly worse than most other mixers, thus restricting them to receiver designs where sensitivity may not be a primary concern. If the noise performance can be addressed in some way, then these mixers could be an excellent alternative for many applications. Another potential area for future work is to take the time-varying power-series analysis presented here and expand it into a Volterra analysis. A Volterra analysis of the core could take into account parasitics and therefore provide accurate high-frequency results. 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CMOS bulk-driven mixers with passive baluns Van Vorst, Daryl 2008
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Title | CMOS bulk-driven mixers with passive baluns |
Creator |
Van Vorst, Daryl |
Publisher | University of British Columbia |
Date Issued | 2008 |
Description | The design, simulation, and measurement of two bulk-driven down-conversion mixers with on-chip transformer baluns in 0.18 μm CMOS is presented. Applying either the RF signal or the local oscillator (LO) signal to the bulk connection of the transistors allows the amplification and switching stages of a conventional mixer to be combined into a single stage, thus improving the voltage headroom of the mixer. The addition of a transformer balun to the mixers improves the input impedance match, provides passive voltage gain, and performs single-ended to balanced conversion. A semi-analytical power-series analysis of the mixers is also presented. The mixer in which the RF signal is applied to the gates of the mixing transistors achieves a measured input-referred 1-dB compression point (P1dB) of −14 dBm, an input-referred third-order intercept point (IIP3) of −5.2 dBm, a gain of 13.6 dB, a noise figure (NF) of 26 dB, and an LO-to-RF isolation of 50 dB. The overall performance of both mixers is found to be comparable with other CMOS mixers, but with a higher noise figure (which can be mitigated with a high gain low-noise amplifier (LNA)). |
Extent | 1101985 bytes |
Subject |
CMOS Bulk-driven mixer Body-effect Transformer balun |
Genre |
Thesis/Dissertation |
Type |
Text |
FileFormat | application/pdf |
Language | eng |
Date Available | 2008-07-16 |
Provider | Vancouver : University of British Columbia Library |
Rights | Attribution-NonCommercial-NoDerivatives 4.0 International |
DOI | 10.14288/1.0065575 |
URI | http://hdl.handle.net/2429/1015 |
Degree |
Master of Applied Science - MASc |
Program |
Electrical and Computer Engineering |
Affiliation |
Applied Science, Faculty of Electrical and Computer Engineering, Department of |
Degree Grantor | University of British Columbia |
GraduationDate | 2008-11 |
Campus |
UBCV |
Scholarly Level | Graduate |
Rights URI | http://creativecommons.org/licenses/by-nc-nd/4.0/ |
AggregatedSourceRepository | DSpace |
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